Searched refs:ref_state (Results 1 - 7 of 7) sorted by relevance

/linux-master/drivers/net/ethernet/intel/ice/
H A Dice_dpll.h42 * @ref_state: state of dpll reference signals
58 u8 ref_state; member in struct:ice_dpll
H A Dice_common.h221 ice_aq_get_cgu_dpll_status(struct ice_hw *hw, u8 dpll_num, u8 *ref_state,
225 ice_aq_set_cgu_dpll_config(struct ice_hw *hw, u8 dpll_num, u8 ref_state,
H A Dice_ptp_hw.h280 u8 *ref_state, u8 *eec_mode, s64 *phase_offset,
H A Dice_common.c5124 * @ref_state: Reference clock state
5134 ice_aq_get_cgu_dpll_status(struct ice_hw *hw, u8 dpll_num, u8 *ref_state, argument
5148 *ref_state = cmd->ref_state;
5165 * @ref_state: Reference clock state
5173 ice_aq_set_cgu_dpll_config(struct ice_hw *hw, u8 dpll_num, u8 ref_state, argument
5182 cmd->ref_state = ref_state;
H A Dice_ptp_hw.c3846 * @ref_state: reference clock state
3852 * 'pin', 'ref_state', 'eec_mode' and 'phase_offset' parameters are used to
3859 u8 *ref_state, u8 *eec_mode, s64 *phase_offset,
3877 if (ref_state)
3878 *ref_state = hw_ref_state;
3857 ice_get_cgu_state(struct ice_hw *hw, u8 dpll_idx, enum dpll_lock_status last_dpll_state, u8 *pin, u8 *ref_state, u8 *eec_mode, s64 *phase_offset, enum dpll_lock_status *dpll_state) argument
H A Dice_adminq_cmd.h2255 u8 ref_state; member in struct:ice_aqc_get_cgu_dpll_status
2290 u8 ref_state; member in struct:ice_aqc_set_cgu_dpll_config
H A Dice_dpll.c1306 &d->input_idx, &d->ref_state, &d->eec_mode,

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