Searched refs:ras (Results 1 - 25 of 88) sorted by relevance

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/linux-master/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_mmhub.c27 struct amdgpu_mmhub_ras *ras; local
29 if (!adev->mmhub.ras)
32 ras = adev->mmhub.ras;
33 err = amdgpu_ras_register_ras_block(adev, &ras->ras_block);
35 dev_err(adev->dev, "Failed to register mmhub ras block!\n");
39 strcpy(ras->ras_block.ras_comm.name, "mmhub");
40 ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__MMHUB;
41 ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
42 adev->mmhub.ras_if = &ras
[all...]
H A Damdgpu_hdp.c29 struct amdgpu_hdp_ras *ras; local
31 if (!adev->hdp.ras)
34 ras = adev->hdp.ras;
35 err = amdgpu_ras_register_ras_block(adev, &ras->ras_block);
37 dev_err(adev->dev, "Failed to register hdp ras block!\n");
41 strcpy(ras->ras_block.ras_comm.name, "hdp");
42 ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__HDP;
43 ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
44 adev->hdp.ras_if = &ras
[all...]
H A Damdgpu_nbio.c28 struct amdgpu_nbio_ras *ras; local
30 if (!adev->nbio.ras)
33 ras = adev->nbio.ras;
34 err = amdgpu_ras_register_ras_block(adev, &ras->ras_block);
36 dev_err(adev->dev, "Failed to register pcie_bif ras block!\n");
40 strcpy(ras->ras_block.ras_comm.name, "pcie_bif");
41 ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__PCIE_BIF;
42 ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
43 adev->nbio.ras_if = &ras
[all...]
H A Damdgpu_umc.c104 if (adev->umc.ras && adev->umc.ras->ras_block.hw_ops &&
105 adev->umc.ras->ras_block.hw_ops->query_ras_error_count)
106 adev->umc.ras->ras_block.hw_ops->query_ras_error_count(adev, ras_error_status);
108 if (adev->umc.ras && adev->umc.ras->ras_block.hw_ops &&
109 adev->umc.ras->ras_block.hw_ops->query_ras_error_address &&
125 adev->umc.ras->ras_block.hw_ops->query_ras_error_address(adev, ras_error_status);
129 if (adev->umc.ras &&
130 adev->umc.ras
320 struct amdgpu_umc_ras *ras; local
[all...]
H A Damdgpu_mca.c33 if (adev->umc.ras->check_ecc_err_status)
34 return adev->umc.ras->check_ecc_err_status(adev,
87 struct amdgpu_mca_ras_block *ras; local
89 if (!adev->mca.mp0.ras)
92 ras = adev->mca.mp0.ras;
94 err = amdgpu_ras_register_ras_block(adev, &ras->ras_block);
96 dev_err(adev->dev, "Failed to register mca.mp0 ras block!\n");
100 strcpy(ras->ras_block.ras_comm.name, "mca.mp0");
101 ras
111 struct amdgpu_mca_ras_block *ras; local
135 struct amdgpu_mca_ras_block *ras; local
[all...]
H A Damdgpu_hdp.h43 struct amdgpu_hdp_ras *ras; member in struct:amdgpu_hdp
H A Damdgpu_sdma.c298 struct amdgpu_sdma_ras *ras = NULL; local
300 /* adev->sdma.ras is NULL, which means sdma does not
301 * support ras function, then do nothing here.
303 if (!adev->sdma.ras)
306 ras = adev->sdma.ras;
308 err = amdgpu_ras_register_ras_block(adev, &ras->ras_block);
310 dev_err(adev->dev, "Failed to register sdma ras block!\n");
314 strcpy(ras->ras_block.ras_comm.name, "sdma");
315 ras
[all...]
H A Damdgpu_jpeg.c310 struct amdgpu_jpeg_ras *ras; local
312 if (!adev->jpeg.ras)
315 ras = adev->jpeg.ras;
316 err = amdgpu_ras_register_ras_block(adev, &ras->ras_block);
318 dev_err(adev->dev, "Failed to register jpeg ras block!\n");
322 strcpy(ras->ras_block.ras_comm.name, "jpeg");
323 ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__JPEG;
324 ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__POISON;
325 adev->jpeg.ras_if = &ras
[all...]
H A Damdgpu_mmhub.h71 struct amdgpu_mmhub_ras *ras; member in struct:amdgpu_mmhub
H A Dgfx_v11_0_3.c60 dev_err(adev->dev, "Gfx or sdma ras block not initialized, rlc_status0:0x%x.\n",
94 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); local
96 ras->gpu_reset_flags |= AMDGPU_RAS_GPU_RESET_MODE2_RESET;
H A Damdgpu_ras_eeprom.c322 DRM_ERROR("Failed to alloc buf to write table ras info\n");
337 DRM_ERROR("Failed to write EEPROM table ras info:%d", res);
426 if (adev->umc.ras &&
427 adev->umc.ras->set_eeprom_table_version)
428 adev->umc.ras->set_eeprom_table_version(hdr);
721 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); local
729 control->ras_num_recs >= ras->bad_page_cnt_threshold) {
732 control->ras_num_recs, ras->bad_page_cnt_threshold);
784 control->ras_num_recs < ras->bad_page_cnt_threshold)
785 control->tbl_rai.health_percent = ((ras
1008 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); local
1065 struct amdgpu_ras *ras = container_of(control, struct amdgpu_ras, local
1077 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); local
1192 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); local
1316 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); local
[all...]
H A Dumc_v6_7.c101 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); local
109 mc_umc_status = ras->umc_ecc.ecc[eccinfo_table_idx].mca_umc_status;
116 if (ras->umc_ecc.record_ce_addr_supported) {
121 err_addr = ras->umc_ecc.ecc[eccinfo_table_idx].mca_ceumc_addr;
143 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); local
150 mc_umc_status = ras->umc_ecc.ecc[eccinfo_table_idx].mca_umc_status;
228 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); local
232 mc_umc_status = ras->umc_ecc.ecc[eccinfo_table_idx].mca_umc_status;
244 err_addr = ras->umc_ecc.ecc[eccinfo_table_idx].mca_umc_addr;
H A Damdgpu_gfx.c509 struct amdgpu_ras *ras; local
533 * during ras recovery in suspend stage for gfx9.4.3
541 ras = amdgpu_ras_get_context(adev);
543 ras && (atomic_read(&ras->in_recovery) || hive_ras_recovery)) {
843 struct amdgpu_gfx_ras *ras = NULL; local
845 /* adev->gfx.ras is NULL, which means gfx does not
846 * support ras function, then do nothing here.
848 if (!adev->gfx.ras)
851 ras
[all...]
H A Daldebaran.c362 if (tmp_adev->sdma.ras &&
363 tmp_adev->sdma.ras->ras_block.ras_late_init) {
364 r = tmp_adev->sdma.ras->ras_block.ras_late_init(tmp_adev,
365 &tmp_adev->sdma.ras->ras_block.ras_comm);
372 if (tmp_adev->gfx.ras &&
373 tmp_adev->gfx.ras->ras_block.ras_late_init) {
374 r = tmp_adev->gfx.ras->ras_block.ras_late_init(tmp_adev,
375 &tmp_adev->gfx.ras->ras_block.ras_comm);
H A Damdgpu_ras.c49 static const char *RAS_FS_NAME = "ras";
89 /* ras block link */
199 dev_warn(adev->dev, " echo 1 > /sys/kernel/debug/dri/0/ras/ras_eeprom_reset\n");
429 * echo "disable <block>" > /sys/kernel/debug/dri/<N>/ras/ras_ctrl
430 * echo "enable <block> <error>" > /sys/kernel/debug/dri/<N>/ras/ras_ctrl
431 * echo "inject <block> <error> <sub-block> <address> <value> <mask>" > /sys/kernel/debug/dri/<N>/ras/ras_ctrl
455 * echo inject umc ue 0x0 0x0 0x0 > /sys/kernel/debug/dri/0/ras/ras_ctrl
456 * echo inject umc ce 0 0 0 3 > /sys/kernel/debug/dri/0/ras/ras_ctrl
457 * echo disable umc > /sys/kernel/debug/dri/0/ras/ras_ctrl
461 * To check disable/enable, see "ras" feature
1015 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); local
1391 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); local
2389 struct amdgpu_ras *ras = local
3457 struct amdgpu_ras *ras; local
3468 struct amdgpu_ras *ras; local
3478 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); local
3637 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); local
3665 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); local
[all...]
H A Dumc_v8_7.c56 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); local
63 mc_umc_status = ras->umc_ecc.ecc[eccinfo_table_idx].mca_umc_status;
75 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); local
80 mc_umc_status = ras->umc_ecc.ecc[eccinfo_table_idx].mca_umc_status;
137 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); local
140 mc_umc_status = ras->umc_ecc.ecc[eccinfo_table_idx].mca_umc_status;
152 err_addr = ras->umc_ecc.ecc[eccinfo_table_idx].mca_umc_addr;
H A Dumc_v8_10.c341 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); local
349 ecc_ce_cnt = ras->umc_ecc.ecc[eccinfo_table_idx].ce_count_lo_chip;
360 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); local
368 mc_umc_status = ras->umc_ecc.ecc[eccinfo_table_idx].mca_umc_status;
408 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); local
415 mc_umc_status = ras->umc_ecc.ecc[eccinfo_table_idx].mca_umc_status;
428 err_addr = ras->umc_ecc.ecc[eccinfo_table_idx].mca_umc_addr;
H A Damdgpu_jpeg.h95 struct amdgpu_jpeg_ras *ras; member in struct:amdgpu_jpeg
/linux-master/drivers/ras/
H A DMakefile2 obj-$(CONFIG_RAS) += ras.o
H A Dras.c10 #include <linux/ras.h>
45 #define TRACE_INCLUDE_PATH ../../include/ras
46 #include <ras/ras_event.h>
86 __setup("ras", parse_ras_param);
H A Ddebugfs.c3 #include <linux/ras.h>
64 ras_debugfs_dir = debugfs_create_dir("ras", NULL);
/linux-master/arch/powerpc/platforms/cell/
H A DMakefile6 obj-$(CONFIG_CBE_RAS) += ras.o
/linux-master/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
H A Dvega20_baco.c75 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); local
86 if (!ras || !adev->ras_enabled) {
/linux-master/include/linux/netfilter/
H A Dnf_conntrack_h323_asn1.h91 int DecodeRasMessage(unsigned char *buf, size_t sz, RasMessage * ras);
/linux-master/arch/powerpc/platforms/pseries/
H A DMakefile8 setup.o iommu.o event_sources.o ras.o \

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