Searched refs:radeon_get_ib_value (Results 1 - 9 of 9) sorted by relevance

/linux-master/drivers/gpu/drm/radeon/
H A Dr600_cs.c848 wait_reg_mem_info = radeon_get_ib_value(p, wait_reg_mem.idx + 1);
864 if ((radeon_get_ib_value(p, wait_reg_mem.idx + 2) << 2) != vline_status[0]) {
869 if (radeon_get_ib_value(p, wait_reg_mem.idx + 5) != RADEON_VLINE_STAT) {
883 header = radeon_get_ib_value(p, h_idx);
884 crtc_id = radeon_get_ib_value(p, h_idx + 2 + 7 + 1);
1005 /*tmp =radeon_get_ib_value(p, idx);
1023 track->sq_config = radeon_get_ib_value(p, idx);
1026 track->db_depth_control = radeon_get_ib_value(p, idx);
1038 track->db_depth_info = radeon_get_ib_value(p, idx);
1049 track->db_depth_info = radeon_get_ib_value(
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H A Devergreen_cs.c763 texdw[0] = radeon_get_ib_value(p, idx + 0);
764 texdw[1] = radeon_get_ib_value(p, idx + 1);
765 texdw[2] = radeon_get_ib_value(p, idx + 2);
766 texdw[3] = radeon_get_ib_value(p, idx + 3);
767 texdw[4] = radeon_get_ib_value(p, idx + 4);
768 texdw[5] = radeon_get_ib_value(p, idx + 5);
769 texdw[6] = radeon_get_ib_value(p, idx + 6);
770 texdw[7] = radeon_get_ib_value(p, idx + 7);
1131 /*tmp =radeon_get_ib_value(p, idx);
1151 track->db_depth_control = radeon_get_ib_value(
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H A Dradeon_vce.c478 offset = radeon_get_ib_value(p, lo);
479 idx = radeon_get_ib_value(p, hi);
565 uint32_t len = radeon_get_ib_value(p, p->idx);
566 uint32_t cmd = radeon_get_ib_value(p, p->idx + 1);
582 handle = radeon_get_ib_value(p, p->idx + 2);
601 *size = radeon_get_ib_value(p, p->idx + 8) *
602 radeon_get_ib_value(p, p->idx + 10) *
638 tmp = radeon_get_ib_value(p, p->idx + 4);
H A Dr300.c639 idx_value = radeon_get_ib_value(p, idx);
1196 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset);
1207 if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) {
1211 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1222 if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) {
1226 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1234 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1241 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1248 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1255 track->vap_vf_cntl = radeon_get_ib_value(
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H A Dr100.c1286 value = radeon_get_ib_value(p, idx);
1322 c = radeon_get_ib_value(p, idx++) & 0x1F;
1338 idx_value = radeon_get_ib_value(p, idx);
1339 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset);
1351 ib[idx+2] = radeon_get_ib_value(p, idx + 2) + ((u32)reloc->gpu_offset);
1364 idx_value = radeon_get_ib_value(p, idx);
1365 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset);
1456 if (radeon_get_ib_value(p, waitreloc.idx + 1) != RADEON_WAIT_CRTC_VLINE) {
1470 header = radeon_get_ib_value(p, h_idx);
1471 crtc_id = radeon_get_ib_value(
[all...]
H A Dradeon_cs.c756 header = radeon_get_ib_value(p, idx);
792 printk("\t0x%08x <---\n", radeon_get_ib_value(p, i));
794 printk("\t0x%08x\n", radeon_get_ib_value(p, i));
875 idx = radeon_get_ib_value(p, p3reloc.idx + 1);
H A Dradeon_uvd.c572 offset = radeon_get_ib_value(p, data0);
573 idx = radeon_get_ib_value(p, data1);
588 cmd = radeon_get_ib_value(p, p->idx) >> 1;
H A Dr200.c161 idx_value = radeon_get_ib_value(p, idx);
H A Dradeon.h1050 static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx) function

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