Searched refs:pll2 (Results 1 - 13 of 13) sorted by relevance

/linux-master/drivers/mfd/
H A Dsm501.c116 static unsigned long decode_div(unsigned long pll2, unsigned long val, argument
121 pll2 = 288 * MHZ;
123 return pll2 / div_tab[(val >> lshft) & mask];
140 unsigned long pll2 = 0; local
144 pll2 = 336 * MHZ;
147 pll2 = 288 * MHZ;
150 pll2 = 240 * MHZ;
153 pll2 = 192 * MHZ;
157 sdclk0 = (misct & (1<<12)) ? pll2 : 288 * MHZ;
160 sdclk1 = (misct & (1<<20)) ? pll2
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/linux-master/drivers/clk/sunxi/
H A DMakefile12 obj-$(CONFIG_CLK_SUNXI_CLOCKS) += clk-a10-pll2.o
H A Dclk-a10-pll2.c16 #include <dt-bindings/clock/sun4i-a10-pll2.h>
62 prediv_clk = clk_register_divider(NULL, "pll2-prediv",
95 base_clk = clk_register_composite(NULL, "pll2-base",
186 CLK_OF_DECLARE(sun4i_a10_pll2, "allwinner,sun4i-a10-pll2-clk",
194 CLK_OF_DECLARE(sun5i_a13_pll2, "allwinner,sun5i-a13-pll2-clk",
/linux-master/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/
H A Dnv04.c208 uint32_t pll2 = (oldpll2 & 0x7fff0000) | 1 << 31 | pv->NM2; local
214 /* model specific additions to generic pll1 and pll2 set up above */
218 pll2 = 0;
227 pll2 |= 0x011f;
233 if (oldpll1 == pll1 && oldpll2 == pll2)
266 nvkm_wr32(device, reg2, pll2);
/linux-master/drivers/gpu/drm/hisilicon/hibmc/
H A Dhibmc_drm_de.c284 static void get_pll_config(u64 x, u64 y, u32 *pll1, u32 *pll2) argument
293 *pll2 = hibmc_pll_table[i].pll2_config_value;
300 *pll2 = CRT_PLL2_HS_25MHZ;
316 u32 pll2; /* bit[63:32] of PLL */ local
322 get_pll_config(x, y, &pll1, &pll2);
323 writel(pll2, priv->mmio + CRT_PLL2_HS);
/linux-master/drivers/gpu/drm/nouveau/dispnv04/
H A Dhw.c133 uint32_t pll2, struct nvkm_pll_vals *pllvals)
137 /* to force parsing as single stage (i.e. nv40 vplls) pass pll2 as 0 */
144 pllvals->NM1 = pll2 & 0xffff;
147 pllvals->NM2 = pll2 >> 16;
150 if (nv_two_reg_pll(dev) && pll2 & NV31_RAMDAC_ENABLE_VCO2)
151 pllvals->NM2 = pll2 & 0xffff;
170 uint32_t reg1, pll1, pll2 = 0; local
180 pll2 = nvif_rd32(device, reg1 + 4);
184 pll2 = nvif_rd32(device, reg2);
193 pll2
132 nouveau_hw_decode_pll(struct drm_device *dev, uint32_t reg1, uint32_t pll1, uint32_t pll2, struct nvkm_pll_vals *pllvals) argument
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/linux-master/drivers/gpu/drm/i915/display/
H A Dintel_dpll_mgr.h212 u32 ebb0, ebb4, pll0, pll1, pll2, pll3, pll6, pll8, pll9, pll10, pcsdw12; member in struct:intel_dpll_hw_state
H A Dintel_dpll_mgr.c2034 PORT_PLL_M2_FRAC_MASK, pll->state.hw_state.pll2);
2149 hw_state->pll2 = intel_de_read(i915, BXT_PORT_PLL(phy, ch, 2));
2150 hw_state->pll2 &= PORT_PLL_M2_FRAC_MASK;
2289 dpll_hw_state->pll2 = PORT_PLL_M2_FRAC(clk_div->m2 & 0x3fffff);
2321 clock.m2 |= REG_FIELD_GET(PORT_PLL_M2_FRAC_MASK, pll_state->pll2);
2409 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
2415 hw_state->pll2,
2431 a->pll2 == b->pll2 &&
/linux-master/drivers/clk/mxs/
H A Dclk-imx28.c133 ref_xtal, pll0, pll1, pll2, ref_cpu, ref_emi, ref_io0, ref_io1, enumerator in enum:imx28_clk
170 clks[pll2] = mxs_clk_pll("pll2", "ref_xtal", PLL2CTRL0, 23, 50000000);
231 clks[enet_out] = clk_register_gate(NULL, "enet_out", "pll2", 0, ENET, 18, 0, &mxs_lock);
/linux-master/drivers/gpu/drm/tegra/
H A Dsor.c369 unsigned int pll2; member in struct:tegra_sor_regs
1453 value = tegra_sor_readl(sor, sor->soc->regs->pll2);
1455 tegra_sor_writel(sor, value, sor->soc->regs->pll2);
1463 value = tegra_sor_readl(sor, sor->soc->regs->pll2);
1466 tegra_sor_writel(sor, value, sor->soc->regs->pll2);
2285 value = tegra_sor_readl(sor, sor->soc->regs->pll2);
2287 tegra_sor_writel(sor, value, sor->soc->regs->pll2);
2300 value = tegra_sor_readl(sor, sor->soc->regs->pll2);
2302 tegra_sor_writel(sor, value, sor->soc->regs->pll2);
2306 value = tegra_sor_readl(sor, sor->soc->regs->pll2);
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/linux-master/drivers/media/i2c/
H A Dov7251.c109 const struct ov7251_pll2_cfg *pll2; member in struct:ov7251_pll_cfgs
218 .pll2 = &ov7251_pll2_cfg_19_2_mhz,
226 .pll2 = &ov7251_pll2_cfg_24_mhz,
840 configs->pll2->pre_div);
845 configs->pll2->mult);
850 configs->pll2->div);
855 configs->pll2->sys_div);
860 configs->pll2->adc_div);
/linux-master/sound/soc/codecs/
H A Dtscs454.c132 struct pll pll2; member in struct:tscs454
293 pll_init(&tscs454->pll2, 2);
440 mutex_lock(&tscs454->pll2.lock);
457 mutex_unlock(&tscs454->pll2.lock);
689 mutex_lock(&tscs454->pll2.lock);
690 users = tscs454->pll2.users;
691 mutex_unlock(&tscs454->pll2.lock);
3189 aif->pll = &tscs454->pll2;
3202 tscs454->internal_rate.pll = &tscs454->pll2;
/linux-master/drivers/clk/qcom/
H A Dmmcc-msm8960.c44 static struct clk_pll pll2 = { variable in typeref:struct:clk_pll
53 .name = "pll2",
103 { .hw = &pll2.clkr.hw },
116 { .hw = &pll2.clkr.hw },
130 { .hw = &pll2.clkr.hw },
2801 [PLL2] = &pll2.clkr,
2977 [PLL2] = &pll2.clkr,

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