/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn20/ |
H A D | dcn20_fpu.h | 33 display_e2e_pipe_params_st *pipes); 37 display_e2e_pipe_params_st *pipes, 41 display_e2e_pipe_params_st *pipes, 46 display_e2e_pipe_params_st *pipes, 50 display_e2e_pipe_params_st *pipes, 65 bool fast_validate, display_e2e_pipe_params_st *pipes); 77 display_e2e_pipe_params_st *pipes, 80 fast_validate, display_e2e_pipe_params_st *pipes); 87 display_e2e_pipe_params_st *pipes);
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H A D | dcn20_fpu.c | 992 display_e2e_pipe_params_st *pipes) 1005 pipes[pipe_cnt].dout.wb_enable = (wb_info->wb_enabled == true) ? 1 : 0; 1006 pipes[pipe_cnt].dout.num_active_wb++; 1007 pipes[pipe_cnt].dout.wb.wb_src_height = wb_info->dwb_params.cnv_params.crop_height; 1008 pipes[pipe_cnt].dout.wb.wb_src_width = wb_info->dwb_params.cnv_params.crop_width; 1009 pipes[pipe_cnt].dout.wb.wb_dst_width = wb_info->dwb_params.dest_width; 1010 pipes[pipe_cnt].dout.wb.wb_dst_height = wb_info->dwb_params.dest_height; 1011 pipes[pipe_cnt].dout.wb.wb_htaps_luma = 1; 1012 pipes[pipe_cnt].dout.wb.wb_vtaps_luma = 1; 1013 pipes[pipe_cn 990 dcn20_populate_dml_writeback_from_context(struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes) argument 1030 dcn20_fpu_set_wb_arb_params(struct mcif_arb_params *wb_arb_params, struct dc_state *context, display_e2e_pipe_params_st *pipes, int pipe_cnt, int i) argument 1137 dcn20_calculate_dlg_params(struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes, int pipe_cnt, int vlevel) argument 1311 dcn20_populate_dml_pipes_from_context(struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes, bool fast_validate) argument 1725 dcn20_calculate_wm(struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes, int *out_pipe_cnt, int *pipe_split_from, int vlevel, bool fast_validate) argument 2023 dcn20_validate_bandwidth_internal(struct dc *dc, struct dc_state *context, bool fast_validate, display_e2e_pipe_params_st *pipes) argument 2073 dcn20_validate_bandwidth_fp(struct dc *dc, struct dc_state *context, bool fast_validate, display_e2e_pipe_params_st *pipes) argument 2150 dcn21_populate_dml_pipes_from_context(struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes, bool fast_validate) argument 2201 calculate_wm_set_for_vlevel(int vlevel, struct wm_range_table_entry *table_entry, struct dcn_watermarks *wm_set, struct display_mode_lib *dml, display_e2e_pipe_params_st *pipes, int pipe_cnt) argument 2231 dcn21_calculate_wm(struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes, int *out_pipe_cnt, int *pipe_split_from, int vlevel_req, bool fast_validate) argument 2315 dcn21_validate_bandwidth_fp(struct dc *dc, struct dc_state *context, bool fast_validate, display_e2e_pipe_params_st *pipes) argument 2470 dcn201_populate_dml_writeback_from_context_fpu(struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes) argument [all...] |
/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn30/ |
H A D | dcn30_fpu.h | 36 struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes); 40 display_e2e_pipe_params_st *pipes, 48 display_e2e_pipe_params_st *pipes, 68 display_e2e_pipe_params_st *pipes,
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H A D | dcn30_fpu.c | 258 struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes) 275 pipes[pipe_cnt].dout.wb_enable = 0; 276 pipes[pipe_cnt].dout.num_active_wb = 0; 282 pipes[pipe_cnt].dout.wb_enable = 1; 283 pipes[pipe_cnt].dout.num_active_wb++; 326 pipes[pipe_cnt].pipe.dest.pixel_rate_mhz, 333 pipes[pipe_cnt].pipe.dest.htotal, 338 pipes[pipe_cnt].dout.wb = dout_wb; 349 display_e2e_pipe_params_st *pipes, 358 wb_arb_params->cli_watermark[i] = get_wm_writeback_urgent(dml, pipes, pipe_cn 257 dcn30_fpu_populate_dml_writeback_from_context( struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes) argument 347 dcn30_fpu_set_mcif_arb_params(struct mcif_arb_params *wb_arb_params, struct display_mode_lib *dml, display_e2e_pipe_params_st *pipes, int pipe_cnt, int cur_pipe) argument 379 dcn30_fpu_calculate_wm_and_dlg( struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes, int pipe_cnt, int vlevel) argument 691 dcn30_find_dummy_latency_index_for_fw_based_mclk_switch(struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes, int pipe_cnt, int vlevel) argument [all...] |
/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn314/ |
H A D | dcn314_fpu.h | 37 display_e2e_pipe_params_st *pipes,
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H A D | dcn314_fpu.c | 308 display_e2e_pipe_params_st *pipes, 319 dcn31x_populate_dml_pipes_from_context(dc, context, pipes, fast_validate); 334 pipes[pipe_cnt].pipe.dest.vtotal = pipe->stream->adjust.v_total_min; 336 pipes[pipe_cnt].pipe.dest.vtotal = timing->v_total; 340 pipes[pipe_cnt].pipe.dest.vblank_nom = timing->v_total - pipes[pipe_cnt].pipe.dest.vactive; 341 pipes[pipe_cnt].pipe.dest.vblank_nom = min(pipes[pipe_cnt].pipe.dest.vblank_nom, num_lines); 346 pipes[pipe_cnt].pipe.dest.vblank_nom = 347 max(pipes[pipe_cn 307 dcn314_populate_dml_pipes_from_context_fpu(struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes, bool fast_validate) argument [all...] |
/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn351/ |
H A D | dcn351_fpu.h | 14 display_e2e_pipe_params_st *pipes,
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H A D | dcn351_fpu.c | 472 display_e2e_pipe_params_st *pipes, 481 dcn31_populate_dml_pipes_from_context(dc, context, pipes, 501 pipes[pipe_cnt].pipe.dest.vtotal = 503 pipes[pipe_cnt].pipe.dest.vblank_nom = timing->v_total - 504 pipes[pipe_cnt].pipe.dest.vactive; 507 pipes[pipe_cnt].pipe.dest.vblank_nom = timing->v_total - pipes[pipe_cnt].pipe.dest.vactive; 508 pipes[pipe_cnt].pipe.dest.vblank_nom = min(pipes[pipe_cnt].pipe.dest.vblank_nom, num_lines); 513 pipes[pipe_cn 470 dcn351_populate_dml_pipes_from_context_fpu(struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes, bool fast_validate) argument [all...] |
/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn32/ |
H A D | dcn32_fpu.h | 36 display_e2e_pipe_params_st *pipes, 43 display_e2e_pipe_params_st *pipes, 49 display_e2e_pipe_params_st *pipes, 55 display_e2e_pipe_params_st *pipes, 63 display_e2e_pipe_params_st *pipes, 69 void dcn32_zero_pipe_dcc_fraction(display_e2e_pipe_params_st *pipes,
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H A D | dcn32_fpu.c | 274 display_e2e_pipe_params_st *pipes, 290 dcn32_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, false); 292 /* for subvp + DRR case, if subvp pipes are still present we support pstate */ 319 * dcn32_helper_populate_phantom_dlg_params - Get DLG params for phantom pipes 323 * @pipes: [in] DML pipe params array 326 * This function must be called AFTER the phantom pipes are added to context 327 * and run through DML (so that the DLG params for the phantom pipes can be 328 * populated), and BEFORE we program the timing for the phantom pipes. 332 display_e2e_pipe_params_st *pipes, 346 pipes[pipe_id 272 dcn32_find_dummy_latency_index_for_fw_based_mclk_switch(struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes, int pipe_cnt, int vlevel) argument 330 dcn32_helper_populate_phantom_dlg_params(struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes, int pipe_cnt) argument 463 dcn32_set_phantom_stream_timing(struct dc *dc, struct dc_state *context, struct pipe_ctx *ref_pipe, struct dc_stream_state *phantom_stream, display_e2e_pipe_params_st *pipes, unsigned int pipe_cnt, unsigned int dc_pipe_idx) argument 1384 try_odm_power_optimization_and_revalidate( struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes, int *split, bool *merge, unsigned int *vlevel, int pipe_cnt) argument 1428 dcn32_full_validate_bw_helper(struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes, int *vlevel, int *split, bool *merge, int *pipe_cnt) argument 1640 dcn32_calculate_dlg_params(struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes, int pipe_cnt, int vlevel) argument 1932 dcn32_internal_validate_bw(struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes, int *pipe_cnt_out, int *vlevel_out, bool fast_validate) argument 2267 dcn32_calculate_wm_and_dlg_fpu(struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes, int pipe_cnt, int vlevel) argument 3326 dcn32_zero_pipe_dcc_fraction(display_e2e_pipe_params_st *pipes, int pipe_cnt) argument [all...] |
/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn31/ |
H A D | dcn31_fpu.h | 34 void dcn31_zero_pipe_dcc_fraction(display_e2e_pipe_params_st *pipes, 42 display_e2e_pipe_params_st *pipes, 56 display_e2e_pipe_params_st *pipes,
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H A D | dcn31_fpu.c | 443 void dcn31_zero_pipe_dcc_fraction(display_e2e_pipe_params_st *pipes, argument 448 pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_luma = 0; 449 pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_chroma = 0; 482 display_e2e_pipe_params_st *pipes, 503 pipes[0].clks_cfg.voltage = vlevel; 504 pipes[0].clks_cfg.dcfclk_mhz = dcfclk; 505 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz; 513 context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 514 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 515 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cn 480 dcn31_calculate_wm_and_dlg_fp( struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes, int pipe_cnt, int vlevel) argument [all...] |
/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn30/ |
H A D | dcn30_resource.h | 51 display_e2e_pipe_params_st *pipes, 64 display_e2e_pipe_params_st *pipes, 71 display_e2e_pipe_params_st *pipes, 76 struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes); 80 display_e2e_pipe_params_st *pipes, 106 display_e2e_pipe_params_st *pipes, int pipe_cnt, int vlevel);
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/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn301/ |
H A D | dcn301_fpu.h | 39 display_e2e_pipe_params_st *pipes,
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H A D | dcn301_fpu.c | 296 display_e2e_pipe_params_st *pipes, 303 pipes[0].clks_cfg.voltage = vlevel; 304 pipes[0].clks_cfg.dcfclk_mhz = dml->soc.clock_limits[vlevel].dcfclk_mhz; 305 pipes[0].clks_cfg.socclk_mhz = dml->soc.clock_limits[vlevel].socclk_mhz; 311 wm_set->urgent_ns = get_wm_urgent(dml, pipes, pipe_cnt) * 1000; 312 wm_set->cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(dml, pipes, pipe_cnt) * 1000; 313 wm_set->cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(dml, pipes, pipe_cnt) * 1000; 314 wm_set->cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(dml, pipes, pipe_cnt) * 1000; 315 wm_set->pte_meta_urgent_ns = get_wm_memory_trip(dml, pipes, pipe_cnt) * 1000; 316 wm_set->frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(dml, pipes, pipe_cn 292 calculate_wm_set_for_vlevel(int vlevel, struct wm_range_table_entry *table_entry, struct dcn_watermarks *wm_set, struct display_mode_lib *dml, display_e2e_pipe_params_st *pipes, int pipe_cnt) argument 412 dcn301_calculate_wm_and_dlg_fp(struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes, int pipe_cnt, int vlevel_req) argument [all...] |
/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn35/ |
H A D | dcn35_fpu.h | 39 display_e2e_pipe_params_st *pipes,
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H A D | dcn35_fpu.c | 437 display_e2e_pipe_params_st *pipes, 446 dcn31_populate_dml_pipes_from_context(dc, context, pipes, 466 pipes[pipe_cnt].pipe.dest.vtotal = 468 pipes[pipe_cnt].pipe.dest.vblank_nom = timing->v_total - 469 pipes[pipe_cnt].pipe.dest.vactive; 472 pipes[pipe_cnt].pipe.dest.vblank_nom = timing->v_total - pipes[pipe_cnt].pipe.dest.vactive; 473 pipes[pipe_cnt].pipe.dest.vblank_nom = min(pipes[pipe_cnt].pipe.dest.vblank_nom, num_lines); 478 pipes[pipe_cn 435 dcn35_populate_dml_pipes_from_context_fpu(struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes, bool fast_validate) argument [all...] |
/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn31/ |
H A D | dcn31_resource.h | 45 display_e2e_pipe_params_st *pipes, 50 display_e2e_pipe_params_st *pipes, 55 display_e2e_pipe_params_st *pipes); 59 display_e2e_pipe_params_st *pipes,
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/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn21/ |
H A D | dcn21_resource.h | 50 display_e2e_pipe_params_st *pipes,
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/linux-master/drivers/gpu/drm/arm/display/komeda/ |
H A D | komeda_event.c | 110 return (a->pipes[0] | a->pipes[1]) & 120 u64 evts_mask = evts->global | evts->pipes[0] | evts->pipes[1]; 146 komeda_sprintf(&str, ", pipes[0]: "); 147 evt_str(&str, evts->pipes[0]); 148 komeda_sprintf(&str, ", pipes[1]: "); 149 evt_str(&str, evts->pipes[1]);
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/linux-master/drivers/platform/goldfish/ |
H A D | goldfish_pipe.c | 127 /* pipe ID - index into goldfish_pipe_dev::pipes array */ 144 /* doubly linked list of signalled pipes, protected by 177 * - pipes, pipes_capacity 178 * - [*pipes, *pipes + pipes_capacity) - array data 183 * in all allocated pipes 187 * the only operation that happens often is the signalled pipes array 195 * Array of the pipes of |pipes_capacity| elements, 198 struct goldfish_pipe **pipes; member in struct:goldfish_pipe_dev 204 /* Head of a doubly linked list of signalled pipes */ 663 struct goldfish_pipe **pipes = local [all...] |
/linux-master/drivers/gpu/drm/tidss/ |
H A D | tidss_kms.c | 120 struct pipe pipes[TIDSS_MAX_PORTS]; local 178 pipes[num_pipes].hw_videoport = i; 179 pipes[num_pipes].bridge = bridge; 180 pipes[num_pipes].enc_type = enc_type; 205 tcrtc = tidss_crtc_create(tidss, pipes[i].hw_videoport, 214 ret = tidss_encoder_create(tidss, pipes[i].bridge, 215 pipes[i].enc_type,
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/linux-master/drivers/gpu/drm/arm/display/komeda/d71/ |
H A D | d71_dev.h | 41 struct d71_pipeline *pipes[D71_MAX_PIPELINE]; member in struct:d71_dev
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/linux-master/drivers/gpu/drm/amd/display/dc/link/ |
H A D | link_dpms.h | 42 struct pipe_ctx *pipes[MAX_PIPES]);
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/linux-master/drivers/gpu/drm/amd/display/dc/dml2/ |
H A D | dml2_dc_resource_mgmt.c | 140 struct dc_state *state, unsigned int plane_id, unsigned int *pipes) 161 pipes[num_found++] = mpc_pipe->pipe_idx; 197 // // Verify the number of pipes assigned matches 210 // // TODO: could also do additional verification that the pipes in tree are the same as 256 * However this condition comes with a caveat. We need to ignore pipes that will 351 // We like to pair pipes starting from the higher order indicies for combining 353 // Ignore any pipes that are the preferred or last resort candidate 417 // We like to pair pipes starting from the higher order indicies for combining 419 // Ignore any pipes that are the preferred or last resort candidate 449 static void sort_pipes_for_splitting(struct dc_plane_pipe_pool *pipes) argument 139 find_pipes_assigned_to_plane(struct dml2_context *ctx, struct dc_state *state, unsigned int plane_id, unsigned int *pipes) argument 582 find_pipes_assigned_to_stream(struct dml2_context *ctx, struct dc_state *state, unsigned int stream_id, unsigned int *pipes) argument 611 unsigned int pipes[MAX_PIPES] = {0}; local 649 unsigned int pipes[MAX_PIPES] = {0}; local [all...] |