Searched refs:pipe_plane (Results 1 - 11 of 11) sorted by relevance

/linux-master/drivers/gpu/drm/amd/display/dc/dml2/
H A Ddisplay_mode_util.h73 __DML_DLL_EXPORT__ void dml_calc_pipe_plane_mapping(const struct dml_hw_resource_st *hw, dml_uint_t *pipe_plane);
H A Ddisplay_mode_util.c759 dml_uint_t plane_idx = mode_lib->mp.pipe_plane[pipe_idx];
771 if (plane_idx == mode_lib->mp.pipe_plane[i]) {
782 void dml_calc_pipe_plane_mapping(const struct dml_hw_resource_st *hw, dml_uint_t *pipe_plane) argument
787 pipe_plane[k] = __DML_PIPE_NO_PLANE__;
792 pipe_plane[pipe_idx] = plane_idx;
H A Ddml2_mall_phantom.c257 vba->ActiveDRAMClockChangeLatencyMarginPerState[vba->VoltageLevel][vba->maxMpcComb][vba->pipe_plane[pipe_idx]] <= 0) {
623 if (vba->ActiveDRAMClockChangeLatencyMargin[vba->pipe_plane[pipe_idx]] > 0 &&
H A Ddisplay_mode_core_structs.h1077 dml_uint_t pipe_plane[__DML_NUM_PLANES__]; // <brief used mainly by dv to map the pipe inst to plane index within DML core; the plane idx of a pipe member in struct:mode_program_st
H A Ddisplay_mode_core.c8296 dml_calc_pipe_plane_mapping(&mode_lib->ms.cache_display_cfg.hw, mode_lib->mp.pipe_plane);
10186 dml_uint_t plane_idx = mode_lib->mp.pipe_plane[pipe_idx];
10194 plane_idx = mode_lib->mp.pipe_plane[surface_idx]; \
/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn20/
H A Ddcn20_resource.c1916 int pipe_plane = v->pipe_plane[pipe_idx]; local
1923 if (split4mpc || v->NoOfDPP[vlevel][max_mpc_comb][pipe_plane] == 4)
1925 else if (force_split || v->NoOfDPP[vlevel][max_mpc_comb][pipe_plane] == 2)
1939 v->ODMCombineEnablePerState[vlevel][pipe_plane] = dm_odm_combine_mode_2to1;
1943 v->ODMCombineEnablePerState[vlevel][pipe_plane] = dm_odm_combine_mode_4to1;
1950 v->ODMCombineEnabled[pipe_plane] =
1951 v->ODMCombineEnablePerState[vlevel][pipe_plane];
1953 if (v->ODMCombineEnabled[pipe_plane] == dm_odm_combine_mode_disabled) {
/linux-master/drivers/gpu/drm/amd/display/dc/dml/
H A Ddisplay_mode_vba.c134 which_plane = mode_lib->vba.pipe_plane[which_pipe]; \
264 if (plane_idx == mode_lib->vba.pipe_plane[i]) {
282 plane_idx = mode_lib->vba.pipe_plane[pipe_idx];
298 plane_idx = mode_lib->vba.pipe_plane[pipe_idx];
545 mode_lib->vba.pipe_plane[j] = mode_lib->vba.NumberOfActivePlanes;
789 mode_lib->vba.pipe_plane[k] =
H A Ddisplay_mode_vba.h589 unsigned int pipe_plane[DC__NUM_DPP__MAX]; member in struct:vba_vars_st
/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn32/
H A Ddcn32_fpu.c517 num_dpp = vba->NoOfDPP[vba->VoltageLevel][vba->maxMpcComb][vba->pipe_plane[pipe_idx]];
518 phantom_vactive += num_dpp > 1 ? vba->meta_row_height[vba->pipe_plane[pipe_idx]] : 0;
631 (vba->ActiveDRAMClockChangeLatencyMarginPerState[vba->VoltageLevel][vba->maxMpcComb][vba->pipe_plane[pipe_idx]] <= 0 ||
632 (vba->ActiveDRAMClockChangeLatencyMarginPerState[vba->VoltageLevel][vba->maxMpcComb][vba->pipe_plane[pipe_idx]] > 0 &&
1059 if (vba->ActiveDRAMClockChangeLatencyMarginPerState[vlevel][vba->maxMpcComb][vba->pipe_plane[pipe_idx]] > 0 &&
1243 odm = vba->ODMCombineEnabled[vba->pipe_plane[dml_pipe_idx]] !=
1729 if (vba->ActiveDRAMClockChangeLatencyMarginPerState[vba->VoltageLevel][vba->maxMpcComb][vba->pipe_plane[pipe_idx]] > 0)
2016 if (vba->ODMCombineEnabled[vba->pipe_plane[pipe_idx]] != dm_odm_combine_mode_disabled
2121 odm = vba->ODMCombineEnabled[vba->pipe_plane[pipe_idx]] != dm_odm_combine_mode_disabled;
3486 if (vba->ActiveDRAMClockChangeLatencyMarginPerState[vba->VoltageLevel][vba->maxMpcComb][vba->pipe_plane[pipe_id
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn30/
H A Ddcn30_resource.c1712 if (vba->ODMCombineEnabled[vba->pipe_plane[pipe_idx]] != dm_odm_combine_mode_disabled
1781 odm = vba->ODMCombineEnabled[vba->pipe_plane[pipe_idx]] != dm_odm_combine_mode_disabled;
/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn21/
H A Ddcn21_resource.c856 if (vba->ODMCombineEnabled[vba->pipe_plane[pipe_idx]] != dm_odm_combine_mode_disabled

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