Searched refs:pfctx (Results 1 - 7 of 7) sorted by last modified time

/linux-master/include/linux/mlx5/
H A Dmlx5_ifc.h10095 u8 pfctx[0x8]; member in struct:mlx5_ifc_pfcc_reg_bits
/linux-master/drivers/net/ethernet/mellanox/mlxsw/
H A Dreg.h5101 * updated based on bit pfctx.
5137 * Note: pfctx and pptx must be mutually exclusive.
5139 MLXSW_ITEM32(reg, pfcc, pfctx, 0x08, 16, 8);
/linux-master/drivers/net/ethernet/mellanox/mlx4/
H A Dport.c1609 u8 pptx, u8 pfctx, u8 pprx, u8 pfcrx)
1622 context->pptx = (pptx * (!pfctx)) << 7;
1623 context->pfctx = pfctx;
1608 mlx4_SET_PORT_general(struct mlx4_dev *dev, u8 port, int mtu, u8 pptx, u8 pfctx, u8 pprx, u8 pfcrx) argument
H A Dmlx4.h803 u8 pfctx; member in struct:mlx4_set_port_general_context
H A Den_main.c70 MLX4_EN_PARM_INT(pfctx, 0, "Priority based Flow Control policy on TX[7:0]."
166 params->prof[i].rx_pause = !(pfcrx || pfctx);
168 params->prof[i].tx_pause = !(pfcrx || pfctx);
169 params->prof[i].tx_ppp = pfctx;
401 if (pfctx > MAX_PFC_TX) {
402 pr_warn("mlx4_en: WARNING: illegal module parameter pfctx 0x%x - should be in range 0-0x%x, will be changed to default (0)\n",
403 pfctx, MAX_PFC_TX);
404 pfctx = 0;
/linux-master/drivers/net/ethernet/mellanox/mlx5/core/
H A Dport.c590 MLX5_SET(pfcc_reg, in, pfctx, pfc_en_tx);
610 *pfc_en_tx = MLX5_GET(pfcc_reg, out, pfctx);
/linux-master/include/linux/mlx4/
H A Ddevice.h1403 u8 pptx, u8 pfctx, u8 pprx, u8 pfcrx);

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