Searched refs:per_ctx (Results 1 - 6 of 6) sorted by relevance

/linux-master/drivers/gpu/drm/i915/gvt/
H A Dscheduler.h81 struct shadow_per_ctx per_ctx; member in struct:intel_shadow_wa_ctx
H A Dscheduler.c600 (~PER_CTX_ADDR_MASK)) | wa_ctx->per_ctx.shadow_gma;
643 wa_ctx->per_ctx.shadow_gma = *((unsigned int *)per_ctx_va + 1);
1636 u32 head, tail, start, ctl, ctx_ctl, per_ctx, indirect_ctx; local
1705 RING_CTX_OFF(bb_per_ctx_ptr.val), &per_ctx, 4);
1726 workload->wa_ctx.per_ctx.guest_gma =
1727 per_ctx & PER_CTX_ADDR_MASK;
1728 workload->wa_ctx.per_ctx.valid = per_ctx & 1;
1729 if (workload->wa_ctx.per_ctx.valid) {
1731 workload->wa_ctx.per_ctx
[all...]
H A Dcmd_parser.c3053 if (!wa_ctx->per_ctx.valid)
3057 per_ctx_start[1] = wa_ctx->per_ctx.guest_gma;
/linux-master/drivers/gpu/drm/i915/gt/
H A Dselftest_lrc.c1583 u32 *cs, bool per_ctx)
1592 (per_ctx ? PAGE_SIZE : 0);
1611 wabb_ctx_setup(struct intel_context *ce, bool per_ctx) argument
1613 u32 *cs = context_wabb(ce, per_ctx);
1617 if (per_ctx)
1623 static bool check_ring_start(struct intel_context *ce, bool per_ctx) argument
1627 (per_ctx ? PAGE_SIZE : 0);
1639 static int wabb_ctx_check(struct intel_context *ce, bool per_ctx) argument
1647 if (!check_ring_start(ce, per_ctx))
1653 static int __lrc_wabb_ctx(struct intel_engine_cs *engine, bool per_ctx) argument
1582 emit_wabb_ctx_canary(const struct intel_context *ce, u32 *cs, bool per_ctx) argument
1709 lrc_wabb_ctx(void *arg, bool per_ctx) argument
[all...]
H A Dintel_engine_types.h96 } indirect_ctx, per_ctx; member in struct:i915_ctx_workarounds
H A Dintel_lrc.c912 if (wa_ctx->per_ctx.size) {
917 (ggtt_offset + wa_ctx->per_ctx.offset) | 0x01;
1036 * per_ctx below determines which WABB section is used.
1041 static u32 *context_wabb(const struct intel_context *ce, bool per_ctx) argument
1050 ptr += per_ctx ? PAGE_SIZE : 0;
1704 * Typically we only have one indirect_ctx and per_ctx batch buffer which are
1879 &wa_ctx->indirect_ctx, &wa_ctx->per_ctx

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