Searched refs:pcw_chg_addr (Results 1 - 2 of 2) sorted by last modified time

/linux-master/drivers/clk/mediatek/
H A Dclk-pll.c117 chg = readl(pll->pcw_chg_addr) |
119 writel(chg, pll->pcw_chg_addr);
300 pll->pcw_chg_addr = base + data->pcw_chg_reg;
302 pll->pcw_chg_addr = pll->base_addr + REG_CON1;
H A Dclk-pll.h69 void __iomem *pcw_chg_addr; member in struct:mtk_clk_pll

Completed in 152 milliseconds