Searched refs:pclk (Results 1 - 25 of 214) sorted by relevance

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/linux-master/drivers/clk/
H A Dclk-xgene.c445 struct xgene_clk *pclk = to_xgene_clk(hw); local
449 if (pclk->lock)
450 spin_lock_irqsave(pclk->lock, flags);
452 if (pclk->param.csr_reg) {
455 data = xgene_clk_read(pclk->param.csr_reg +
456 pclk->param.reg_clk_offset);
457 data |= pclk->param.reg_clk_mask;
458 xgene_clk_write(data, pclk->param.csr_reg +
459 pclk->param.reg_clk_offset);
462 pclk
485 struct xgene_clk *pclk = to_xgene_clk(hw); local
515 struct xgene_clk *pclk = to_xgene_clk(hw); local
535 struct xgene_clk *pclk = to_xgene_clk(hw); local
559 struct xgene_clk *pclk = to_xgene_clk(hw); local
599 struct xgene_clk *pclk = to_xgene_clk(hw); local
[all...]
H A Dclk-conf.c18 struct clk *clk, *pclk; local
40 pclk = of_clk_get_from_provider(&clkspec);
42 if (IS_ERR(pclk)) {
43 if (PTR_ERR(pclk) != -EPROBE_DEFER)
46 return PTR_ERR(pclk);
68 rc = clk_set_parent(clk, pclk);
71 __clk_get_name(clk), __clk_get_name(pclk), rc);
73 clk_put(pclk);
77 clk_put(pclk);
/linux-master/drivers/gpu/drm/nouveau/nvkm/subdev/clk/
H A Dg84.c45 struct nvkm_clk **pclk)
47 return nv50_clk_new_(&g84_clk, device, type, inst, (device->chipset >= 0x94), pclk);
44 g84_clk_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_clk **pclk) argument
H A Dnv04.c76 struct nvkm_clk **pclk)
78 int ret = nvkm_clk_new_(&nv04_clk, device, type, inst, false, pclk);
80 (*pclk)->pll_calc = nv04_clk_pll_calc;
81 (*pclk)->pll_prog = nv04_clk_pll_prog;
75 nv04_clk_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_clk **pclk) argument
/linux-master/drivers/clk/x86/
H A Dclk-pmc-atom.c154 struct clk_plt *pclk; local
158 pclk = devm_kzalloc(&pdev->dev, sizeof(*pclk), GFP_KERNEL);
159 if (!pclk)
168 pclk->hw.init = &init;
169 pclk->reg = pmc_data->base + PMC_CLK_CTL_OFFSET + id * PMC_CLK_CTL_SIZE;
170 spin_lock_init(&pclk->lock);
177 if (pmc_data->critical && plt_clk_is_enabled(&pclk->hw))
180 ret = devm_clk_hw_register(&pdev->dev, &pclk->hw);
182 pclk
197 plt_clk_unregister(struct clk_plt *pclk) argument
207 struct clk_plt_fixed *pclk; local
227 plt_clk_unregister_fixed_rate(struct clk_plt_fixed *pclk) argument
[all...]
/linux-master/drivers/gpu/drm/omapdrm/dss/
H A Dhdmi_common.c52 int hdmi_compute_acr(u32 pclk, u32 sample_freq, u32 *n, u32 *cts) argument
75 if (pclk == 27027000 || pclk == 74250000)
78 if (pclk == 27027000)
85 if (pclk == 27027000)
146 *cts = (pclk/1000) * (*n / 128) * deep_color / (sample_freq / 10);
/linux-master/drivers/video/fbdev/omap2/omapfb/dss/
H A Dhdmi_common.c52 int hdmi_compute_acr(u32 pclk, u32 sample_freq, u32 *n, u32 *cts) argument
75 if (pclk == 27027000 || pclk == 74250000)
78 if (pclk == 27027000)
85 if (pclk == 27027000)
146 *cts = (pclk/1000) * (*n / 128) * deep_color / (sample_freq / 10);
/linux-master/drivers/soc/canaan/
H A Dk210-sysctl.c17 struct clk *pclk; local
23 pclk = devm_clk_get(dev, NULL);
24 if (IS_ERR(pclk))
25 return dev_err_probe(dev, PTR_ERR(pclk),
28 ret = clk_prepare_enable(pclk);
/linux-master/arch/arm/mach-spear/
H A Dspear3xx.c74 struct clk *gpt_clk, *pclk; local
86 pclk = clk_get(NULL, pclk_name);
87 if (IS_ERR(pclk)) {
93 clk_set_parent(gpt_clk, pclk);
95 clk_put(pclk);
H A Dspear13xx.c101 struct clk *gpt_clk, *pclk; local
113 pclk = clk_get(NULL, pclk_name);
114 if (IS_ERR(pclk)) {
120 clk_set_parent(gpt_clk, pclk);
122 clk_put(pclk);
/linux-master/drivers/clk/qcom/
H A Dapcs-msm8916.c85 a53cc->pclk = devm_clk_get(parent, NULL);
86 if (IS_ERR(a53cc->pclk)) {
87 ret = PTR_ERR(a53cc->pclk);
94 ret = clk_notifier_register(a53cc->pclk, &a53cc->clk_nb);
118 clk_notifier_unregister(a53cc->pclk, &a53cc->clk_nb);
126 clk_notifier_unregister(a53cc->pclk, &a53cc->clk_nb);
H A Dapcs-sdx55.c82 a7cc->pclk = devm_clk_get(parent, "pll");
83 if (IS_ERR(a7cc->pclk))
84 return dev_err_probe(dev, PTR_ERR(a7cc->pclk),
88 ret = clk_notifier_register(a7cc->pclk, &a7cc->clk_nb);
119 clk_notifier_unregister(a7cc->pclk, &a7cc->clk_nb);
128 clk_notifier_unregister(a7cc->pclk, &a7cc->clk_nb);
H A Dclk-regmap-mux-div.h24 * @pclk: the input PLL clock
37 struct clk *pclk; member in struct:clk_regmap_mux_div
/linux-master/drivers/net/ethernet/cadence/
H A Dmacb_pci.c62 plat_data.pclk = clk_register_fixed_rate(&pdev->dev, "pclk", NULL, 0,
64 if (IS_ERR(plat_data.pclk)) {
65 err = PTR_ERR(plat_data.pclk);
103 clk_unregister(plat_data.pclk);
114 clk_unregister(plat_data->pclk);
/linux-master/drivers/clocksource/
H A Ddw_apb_timer_of.c21 struct clk *pclk; local
44 pclk = of_clk_get_by_name(np, "pclk");
45 if (!IS_ERR(pclk))
46 if (clk_prepare_enable(pclk))
47 pr_warn("pclk for %pOFn is present, but could not be activated\n",
77 if (!IS_ERR(pclk)) {
78 clk_disable_unprepare(pclk);
79 clk_put(pclk);
H A Dtimer-rockchip.c37 struct clk *pclk; member in struct:rk_timer
131 struct clk *pclk; local
146 pclk = of_clk_get_by_name(np, "pclk");
147 if (IS_ERR(pclk)) {
148 ret = PTR_ERR(pclk);
149 pr_err("Failed to get pclk for '%s'\n", TIMER_NAME);
153 ret = clk_prepare_enable(pclk);
155 pr_err("Failed to enable pclk for '%s'\n", TIMER_NAME);
158 timer->pclk
[all...]
H A Dtimer-microchip-pit64b.c53 * @pclk: PIT64B's peripheral clock
59 struct clk *pclk; member in struct:mchp_pit64b_timer
140 clk_disable_unprepare(timer->pclk);
145 clk_prepare_enable(timer->pclk);
261 * PIT64B timer may be fed by gclk or pclk. When gclk is used its rate has to
262 * be at least 3 times lower that pclk's rate. pclk rate is fixed, gclk rate
263 * could be changed via clock APIs. The chosen clock (pclk or gclk) could be
280 * | |-->pclk -->|-->| | +---------+ +-----+ |
287 * - gclk rate <= pclk rat
[all...]
H A Dnomadik-mtu.c185 struct clk *pclk, struct clk *clk)
193 BUG_ON(clk_prepare_enable(pclk));
251 struct clk *pclk; local
262 pclk = of_clk_get_by_name(node, "apb_pclk");
263 if (IS_ERR(pclk)) {
265 return PTR_ERR(pclk);
280 return nmdk_timer_init(base, irq, pclk, clk);
184 nmdk_timer_init(void __iomem *base, int irq, struct clk *pclk, struct clk *clk) argument
/linux-master/drivers/cpufreq/
H A Dspear-cpufreq.c37 int pclk; local
54 pclk = 0; /* src is sys_syn_clk */
56 pclk = 3; /* src is pll3_clk */
58 pclk = 1; /* src is pll1_clk */
63 sys_pclk = clk_get(NULL, sys_clk_src[pclk]);
65 pr_err("Failed to get %s clock\n", sys_clk_src[pclk]);
H A Dqoriq-cpufreq.c25 * @pclk: the parent clock of cpu
29 struct clk **pclk; member in struct:cpu_data
184 data->pclk = kcalloc(count, sizeof(struct clk *), GFP_KERNEL);
185 if (!data->pclk)
194 data->pclk[i] = clk;
219 kfree(data->pclk);
232 kfree(data->pclk);
246 parent = data->pclk[data->table[index].driver_data];
/linux-master/sound/soc/ux500/
H A Dux500_msp_dai.h58 struct clk *pclk; member in struct:ux500_msp_i2s_drvdata
/linux-master/drivers/clk/pxa/
H A Dclk-pxa.c60 struct pxa_clk *pclk = to_pxa_clk(hw); local
63 if (!pclk->is_in_low_power || pclk->is_in_low_power())
64 fix = &pclk->lp;
66 fix = &pclk->hp;
77 struct pxa_clk *pclk = to_pxa_clk(hw); local
79 if (!pclk->is_in_low_power)
81 return pclk->is_in_low_power() ? 0 : 1;
/linux-master/drivers/pwm/
H A Dpwm-rockchip.c34 struct clk *pclk; member in struct:rockchip_pwm_chip
70 ret = clk_enable(pc->pclk);
97 clk_disable(pc->pclk);
194 ret = clk_enable(pc->pclk);
222 clk_disable(pc->pclk);
324 pc->pclk = devm_clk_get(&pdev->dev, "pclk");
326 pc->pclk = pc->clk;
328 if (IS_ERR(pc->pclk))
329 return dev_err_probe(&pdev->dev, PTR_ERR(pc->pclk), "Ca
[all...]
/linux-master/drivers/rtc/
H A Drtc-ftrtc010.c34 struct clk *pclk; member in struct:ftrtc010_rtc
123 rtc->pclk = devm_clk_get(dev, "PCLK");
124 if (IS_ERR(rtc->pclk)) {
127 ret = clk_prepare_enable(rtc->pclk);
190 clk_disable_unprepare(rtc->pclk);
200 if (!IS_ERR(rtc->pclk))
201 clk_disable_unprepare(rtc->pclk);
/linux-master/sound/soc/stm/
H A Dstm32_sai.c49 clk_disable_unprepare(sai->pclk);
59 ret = clk_prepare_enable(sai->pclk);
175 sai->pclk = devm_clk_get(&pdev->dev, "pclk");
176 if (IS_ERR(sai->pclk))
177 return dev_err_probe(&pdev->dev, PTR_ERR(sai->pclk),
178 "missing bus clock pclk\n");
207 ret = clk_prepare_enable(sai->pclk);
228 clk_disable_unprepare(sai->pclk);

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