drivers/clk/clk-xgene.c

445 	struct xgene_clk *pclk = to_xgene_clk(hw);
449 	if (pclk->lock)
450 		spin_lock_irqsave(pclk->lock, flags);
452 	if (pclk->param.csr_reg) {
455 		data = xgene_clk_read(pclk->param.csr_reg +
456 					pclk->param.reg_clk_offset);
457 		data |= pclk->param.reg_clk_mask;
458 		xgene_clk_write(data, pclk->param.csr_reg +
459 					pclk->param.reg_clk_offset);
462 			pclk->param.reg_clk_offset, pclk->param.reg_clk_mask,
466 		data = xgene_clk_read(pclk->param.csr_reg +
467 					pclk->param.reg_csr_offset);
468 		data &= ~pclk->param.reg_csr_mask;
469 		xgene_clk_write(data, pclk->param.csr_reg +
470 					pclk->param.reg_csr_offset);
473 			pclk->param.reg_csr_offset, pclk->param.reg_csr_mask,
477 	if (pclk->lock)
478 		spin_unlock_irqrestore(pclk->lock, flags);
485 	struct xgene_clk *pclk = to_xgene_clk(hw);
489 	if (pclk->lock)
490 		spin_lock_irqsave(pclk->lock, flags);
492 	if (pclk->param.csr_reg) {
495 		data = xgene_clk_read(pclk->param.csr_reg +
496 					pclk->param.reg_csr_offset);
497 		data |= pclk->param.reg_csr_mask;
498 		xgene_clk_write(data, pclk->param.csr_reg +
499 					pclk->param.reg_csr_offset);
502 		data = xgene_clk_read(pclk->param.csr_reg +
503 					pclk->param.reg_clk_offset);
504 		data &= ~pclk->param.reg_clk_mask;
505 		xgene_clk_write(data, pclk->param.csr_reg +
506 					pclk->param.reg_clk_offset);
509 	if (pclk->lock)
510 		spin_unlock_irqrestore(pclk->lock, flags);
515 	struct xgene_clk *pclk = to_xgene_clk(hw);
518 	if (pclk->param.csr_reg) {
520 		data = xgene_clk_read(pclk->param.csr_reg +
521 					pclk->param.reg_clk_offset);
523 			data & pclk->param.reg_clk_mask ? "enabled" :
529 	return data & pclk->param.reg_clk_mask ? 1 : 0;
535 	struct xgene_clk *pclk = to_xgene_clk(hw);
538 	if (pclk->param.divider_reg) {
539 		data = xgene_clk_read(pclk->param.divider_reg +
540 					pclk->param.reg_divider_offset);
541 		data >>= pclk->param.reg_divider_shift;
542 		data &= (1 << pclk->param.reg_divider_width) - 1;
559 	struct xgene_clk *pclk = to_xgene_clk(hw);
565 	if (pclk->lock)
566 		spin_lock_irqsave(pclk->lock, flags);
568 	if (pclk->param.divider_reg) {
573 		divider &= (1 << pclk->param.reg_divider_width) - 1;
574 		divider <<= pclk->param.reg_divider_shift;
577 		data = xgene_clk_read(pclk->param.divider_reg +
578 				pclk->param.reg_divider_offset);
579 		data &= ~(((1 << pclk->param.reg_divider_width) - 1)
580 				<< pclk->param.reg_divider_shift);
582 		xgene_clk_write(data, pclk->param.divider_reg +
583 					pclk->param.reg_divider_offset);
590 	if (pclk->lock)
591 		spin_unlock_irqrestore(pclk->lock, flags);
599 	struct xgene_clk *pclk = to_xgene_clk(hw);
603 	if (pclk->param.divider_reg) {