Searched refs:parent_rate (Results 1 - 25 of 358) sorted by relevance

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/linux-master/drivers/clk/
H A Dclk-fractional-divider_test.c19 unsigned long rate, parent_rate, parent_rate_before, m, n, max_n; local
29 parent_rate = (max_n + 1) * rate; /* so that it exceeds the maximum divisor */
30 parent_rate_before = parent_rate;
32 clk_fractional_divider_general_approximation(&fd->hw, rate, &parent_rate, &m, &n);
33 KUNIT_ASSERT_EQ(test, parent_rate, parent_rate_before);
48 unsigned long rate, parent_rate, parent_rate_before, m, n, max_m; local
58 parent_rate = rate / (max_m + 1); /* so that it exceeds the maximum numerator */
59 parent_rate_before = parent_rate;
61 clk_fractional_divider_general_approximation(&fd->hw, rate, &parent_rate, &m, &n);
62 KUNIT_ASSERT_EQ(test, parent_rate, parent_rate_befor
77 unsigned long rate, parent_rate, parent_rate_before, m, n, max_n; local
107 unsigned long rate, parent_rate, parent_rate_before, m, n, max_m; local
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H A Dclk-fractional-divider.h11 unsigned long *parent_rate,
H A Dclk-multiplier.c33 unsigned long parent_rate)
36 return DIV_ROUND_CLOSEST(rate, parent_rate);
38 return rate / parent_rate;
42 unsigned long parent_rate)
53 return parent_rate * val;
71 unsigned long parent_rate, current_rate, best_rate = ~0; local
101 parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw),
103 current_rate = parent_rate * i;
108 *best_parent_rate = parent_rate;
116 unsigned long *parent_rate)
31 __get_mult(struct clk_multiplier *mult, unsigned long rate, unsigned long parent_rate) argument
41 clk_multiplier_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) argument
115 clk_multiplier_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *parent_rate) argument
125 clk_multiplier_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) argument
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H A Dclk-loongson2.c84 unsigned long parent_rate)
86 return loongson2_calc_pll_rate(0x0, parent_rate);
94 unsigned long parent_rate)
96 return loongson2_calc_pll_rate(0x10, parent_rate);
104 unsigned long parent_rate)
106 return loongson2_calc_pll_rate(0x20, parent_rate);
114 unsigned long parent_rate)
116 return loongson2_calc_pll_rate(0x30, parent_rate);
124 unsigned long parent_rate)
126 return loongson2_calc_pll_rate(0x40, parent_rate);
83 loongson2_node_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) argument
93 loongson2_ddr_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) argument
103 loongson2_dc_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) argument
113 loongson2_pix0_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) argument
123 loongson2_pix1_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) argument
146 loongson2_boot_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) argument
158 loongson2_apb_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) argument
170 loongson2_usb_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) argument
182 loongson2_sata_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) argument
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H A Dclk-sparx5.c58 static unsigned long s5_calc_freq(unsigned long parent_rate, argument
61 unsigned long rate = parent_rate / conf->div;
76 unsigned long parent_rate,
94 conf->freq = s5_calc_freq(parent_rate, conf);
109 unsigned long parent_rate,
112 if (parent_rate % rate) {
116 div = DIV_ROUND_CLOSEST_ULL(parent_rate, rate);
117 s5_search_fractional(rate, parent_rate, div, &alt1);
124 div = parent_rate / rate;
126 s5_search_fractional(rate, parent_rate, di
75 s5_search_fractional(unsigned long rate, unsigned long parent_rate, int div, struct s5_pll_conf *conf) argument
108 s5_calc_params(unsigned long rate, unsigned long parent_rate, struct s5_pll_conf *conf) argument
165 s5_pll_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) argument
192 s5_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) argument
216 s5_pll_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *parent_rate) argument
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/linux-master/drivers/clk/at91/
H A Dclk-h32mx.c29 unsigned long parent_rate)
36 return parent_rate / 2;
38 if (parent_rate > H32MX_MAX_FREQ)
40 return parent_rate;
44 unsigned long *parent_rate)
48 if (rate > *parent_rate)
49 return *parent_rate;
50 div = *parent_rate / 2;
54 if (rate - div < *parent_rate - rate)
57 return *parent_rate;
28 clk_sama5d4_h32mx_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) argument
43 clk_sama5d4_h32mx_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *parent_rate) argument
60 clk_sama5d4_h32mx_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) argument
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H A Dclk-plldiv.c23 unsigned long parent_rate)
31 return parent_rate / 2;
33 return parent_rate;
37 unsigned long *parent_rate)
41 if (rate > *parent_rate)
42 return *parent_rate;
43 div = *parent_rate / 2;
47 if (rate - div < *parent_rate - rate)
50 return *parent_rate;
54 unsigned long parent_rate)
22 clk_plldiv_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) argument
36 clk_plldiv_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *parent_rate) argument
53 clk_plldiv_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) argument
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H A Dclk-audio-pll.c159 static unsigned long clk_audio_pll_fout(unsigned long parent_rate, argument
162 unsigned long long fr = (unsigned long long)parent_rate * fracr;
170 return parent_rate * (nd + 1) + fr;
174 unsigned long parent_rate)
179 fout = clk_audio_pll_fout(parent_rate, frac->nd, frac->fracr);
188 unsigned long parent_rate)
194 apad_rate = parent_rate / (apad_ck->qdaudio * apad_ck->div);
203 unsigned long parent_rate)
208 apmc_rate = parent_rate / (apmc_ck->qdpmc + 1);
217 unsigned long parent_rate,
173 clk_audio_pll_frac_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) argument
187 clk_audio_pll_pad_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) argument
202 clk_audio_pll_pmc_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) argument
216 clk_audio_pll_frac_compute_frac(unsigned long rate, unsigned long parent_rate, unsigned long *nd, unsigned long *fracr) argument
273 clk_audio_pll_pad_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *parent_rate) argument
324 clk_audio_pll_pmc_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *parent_rate) argument
364 clk_audio_pll_frac_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) argument
387 clk_audio_pll_pad_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) argument
411 clk_audio_pll_pmc_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) argument
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/linux-master/drivers/clk/actions/
H A Dowl-divider.c19 unsigned long *parent_rate)
21 return divider_round_rate(&common->hw, rate, parent_rate,
27 unsigned long *parent_rate)
32 rate, parent_rate);
37 unsigned long parent_rate)
46 return divider_recalc_rate(&common->hw, parent_rate,
53 unsigned long parent_rate)
58 &div->div_hw, parent_rate);
64 unsigned long parent_rate)
69 val = divider_get_val(rate, parent_rate, div_h
16 owl_divider_helper_round_rate(struct owl_clk_common *common, const struct owl_divider_hw *div_hw, unsigned long rate, unsigned long *parent_rate) argument
26 owl_divider_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *parent_rate) argument
35 owl_divider_helper_recalc_rate(struct owl_clk_common *common, const struct owl_divider_hw *div_hw, unsigned long parent_rate) argument
52 owl_divider_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) argument
61 owl_divider_helper_set_rate(const struct owl_clk_common *common, const struct owl_divider_hw *div_hw, unsigned long rate, unsigned long parent_rate) argument
81 owl_divider_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) argument
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H A Dowl-factor.c44 unsigned long rate, unsigned long parent_rate)
51 calc_rate = parent_rate * clkt->mul;
71 unsigned long parent_rate, try_parent_rate, best = 0, cur_rate; local
79 parent_rate = *best_parent_rate;
80 bestval = _get_table_val(clkt, rate, parent_rate);
100 parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw),
102 cur_rate = DIV_ROUND_UP(parent_rate, clkt->div) * clkt->mul;
106 *best_parent_rate = parent_rate;
122 unsigned long *parent_rate)
127 val = owl_clk_val_best(factor_hw, &common->hw, rate, parent_rate);
43 _get_table_val(const struct clk_factor_table *table, unsigned long rate, unsigned long parent_rate) argument
119 owl_factor_helper_round_rate(struct owl_clk_common *common, const struct owl_factor_hw *factor_hw, unsigned long rate, unsigned long *parent_rate) argument
133 owl_factor_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *parent_rate) argument
143 owl_factor_helper_recalc_rate(struct owl_clk_common *common, const struct owl_factor_hw *factor_hw, unsigned long parent_rate) argument
173 owl_factor_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) argument
183 owl_factor_helper_set_rate(const struct owl_clk_common *common, const struct owl_factor_hw *factor_hw, unsigned long rate, unsigned long parent_rate) argument
205 owl_factor_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) argument
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H A Dowl-composite.c72 unsigned long parent_rate)
77 parent_rate);
81 unsigned long parent_rate)
86 rate, parent_rate);
106 unsigned long parent_rate)
112 parent_rate);
116 unsigned long parent_rate)
122 rate, parent_rate);
126 unsigned long *parent_rate)
131 return comp->fix_fact_ops->round_rate(&fix_fact_hw->hw, rate, parent_rate);
71 owl_comp_div_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) argument
80 owl_comp_div_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) argument
105 owl_comp_fact_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) argument
115 owl_comp_fact_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) argument
125 owl_comp_fix_fact_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *parent_rate) argument
134 owl_comp_fix_fact_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) argument
144 owl_comp_fix_fact_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) argument
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/linux-master/drivers/clk/imx/
H A Dclk-pllv3.c112 unsigned long parent_rate)
117 return (div == 1) ? parent_rate * 22 : parent_rate * 20;
123 unsigned long parent_rate = *prate; local
125 return (rate >= parent_rate * 22) ? parent_rate * 22 :
126 parent_rate * 20;
130 unsigned long parent_rate)
135 if (rate == parent_rate * 22)
137 else if (rate == parent_rate * 2
111 clk_pllv3_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) argument
129 clk_pllv3_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) argument
159 clk_pllv3_sys_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) argument
171 unsigned long parent_rate = *prate; local
185 clk_pllv3_sys_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) argument
214 clk_pllv3_av_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) argument
232 unsigned long parent_rate = *prate; local
261 clk_pllv3_av_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) argument
309 clk_pllv3_vf610_mf_to_rate(unsigned long parent_rate, struct clk_pllv3_vf610_mf mf) argument
321 clk_pllv3_vf610_rate_to_mf( unsigned long parent_rate, unsigned long rate) argument
345 clk_pllv3_vf610_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) argument
366 clk_pllv3_vf610_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) argument
396 clk_pllv3_enet_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) argument
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H A Dclk-pllv4.c79 unsigned long parent_rate)
91 temp64 = parent_rate;
95 return (parent_rate * mult) + (u32)temp64;
102 unsigned long parent_rate = *prate; local
111 do_div(temp64, parent_rate);
115 round_rate = parent_rate * mult;
120 round_rate = parent_rate * pllv4_mult_table[i];
130 clk_hw_get_name(hw), rate, parent_rate);
134 if (parent_rate <= MAX_MFD)
135 mfd = parent_rate;
78 clk_pllv4_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) argument
177 clk_pllv4_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) argument
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/linux-master/drivers/clk/sprd/
H A Ddiv.c13 unsigned long *parent_rate)
17 return divider_round_rate(&cd->common.hw, rate, parent_rate, NULL,
23 unsigned long parent_rate)
32 return divider_recalc_rate(&common->hw, parent_rate, val, NULL, 0,
38 unsigned long parent_rate)
42 return sprd_div_helper_recalc_rate(&cd->common, &cd->div, parent_rate);
48 unsigned long parent_rate)
53 val = divider_get_val(rate, parent_rate, NULL,
68 unsigned long parent_rate)
73 rate, parent_rate);
12 sprd_div_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *parent_rate) argument
21 sprd_div_helper_recalc_rate(struct sprd_clk_common *common, const struct sprd_div_internal *div, unsigned long parent_rate) argument
37 sprd_div_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) argument
45 sprd_div_helper_set_rate(const struct sprd_clk_common *common, const struct sprd_div_internal *div, unsigned long rate, unsigned long parent_rate) argument
67 sprd_div_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) argument
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H A Dcomposite.c21 unsigned long parent_rate)
25 return sprd_div_helper_recalc_rate(&cc->common, &cc->div, parent_rate);
29 unsigned long parent_rate)
34 rate, parent_rate);
20 sprd_comp_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) argument
28 sprd_comp_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) argument
/linux-master/include/linux/clk/
H A Danalogbits-wrpll-cln28hpc.h44 * @parent_rate: PLL refclk rate for which values are valid
45 * @max_r: maximum possible R divider value, given @parent_rate
66 unsigned long parent_rate; member in struct:wrpll_cfg
72 unsigned long parent_rate);
77 unsigned long parent_rate);
/linux-master/drivers/clk/analogbits/
H A Dwrpll-cln28hpc.c178 * @parent_rate: PLL input refclk rate (pre-R-divider)
189 unsigned long parent_rate)
193 if (parent_rate > MAX_INPUT_FREQ || parent_rate < MIN_POST_DIVR_FREQ)
196 c->parent_rate = parent_rate;
197 max_r_for_parent = div_u64(parent_rate, MIN_POST_DIVR_FREQ);
200 c->init_r = DIV_ROUND_UP_ULL(parent_rate, MAX_POST_DIVR_FREQ);
209 * @parent_rate: PLL input refclk rate (pre-R-divider)
227 unsigned long parent_rate)
188 __wrpll_update_parent_rate(struct wrpll_cfg *c, unsigned long parent_rate) argument
226 wrpll_configure_for_rate(struct wrpll_cfg *c, u32 target_rate, unsigned long parent_rate) argument
336 wrpll_calc_output_rate(const struct wrpll_cfg *c, unsigned long parent_rate) argument
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/linux-master/drivers/clk/spear/
H A Dclk.c14 unsigned long parent_rate, clk_calc_rate calc_rate, u8 rtbl_cnt,
21 rate = calc_rate(hw, parent_rate, *index);
13 clk_round_rate_index(struct clk_hw *hw, unsigned long drate, unsigned long parent_rate, clk_calc_rate calc_rate, u8 rtbl_cnt, int *index) argument
/linux-master/drivers/clk/nuvoton/
H A Dclk-ma35d1-pll.c82 unsigned long parent_rate)
88 return parent_rate;
94 pll_freq = (u64)parent_rate * n;
99 static unsigned long ma35d1_calc_pll_freq(u8 mode, u32 *reg_ctl, unsigned long parent_rate) argument
105 return parent_rate;
112 pll_freq = (u64)parent_rate * n;
118 pll_freq = div_u64(parent_rate * n, 100 * m * p);
124 unsigned long parent_rate, u32 *reg_ctl,
148 tmp = div_u64(parent_rate, m);
153 fclk = div_u64(parent_rate *
81 ma35d1_calc_smic_pll_freq(u32 pll0_ctl0, unsigned long parent_rate) argument
123 ma35d1_pll_find_closest(struct ma35d1_clk_pll *pll, unsigned long rate, unsigned long parent_rate, u32 *reg_ctl, unsigned long *freq) argument
185 ma35d1_clk_pll_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) argument
221 ma35d1_clk_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) argument
247 ma35d1_clk_pll_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *parent_rate) argument
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/linux-master/drivers/clk/mstar/
H A Dclk-msc313-cpupll.c117 static unsigned long msc313_cpupll_frequencyforreg(u32 reg, unsigned long parent_rate) argument
119 unsigned long long prescaled = ((unsigned long long)parent_rate) * MULTIPLIER;
126 static u32 msc313_cpupll_regforfrequecy(unsigned long rate, unsigned long parent_rate) argument
128 unsigned long long prescaled = ((unsigned long long)parent_rate) * MULTIPLIER;
135 static unsigned long msc313_cpupll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) argument
140 parent_rate);
144 unsigned long *parent_rate)
146 u32 reg = msc313_cpupll_regforfrequecy(rate, *parent_rate);
147 long rounded = msc313_cpupll_frequencyforreg(reg, *parent_rate);
154 rounded = msc313_cpupll_frequencyforreg(reg, *parent_rate);
143 msc313_cpupll_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *parent_rate) argument
159 msc313_cpupll_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) argument
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/linux-master/drivers/clk/tegra/
H A Dclk-utils.c12 int div_frac_get(unsigned long rate, unsigned parent_rate, u8 width, argument
15 u64 divider_ux1 = parent_rate;
/linux-master/drivers/clk/sunxi-ng/
H A Dccu_phase.c17 unsigned int parent_rate, grandparent_rate; local
35 parent_rate = clk_hw_get_rate(parent);
36 if (!parent_rate)
50 parent_div = grandparent_rate / parent_rate;
60 unsigned int parent_rate, grandparent_rate; local
71 parent_rate = clk_hw_get_rate(parent);
72 if (!parent_rate)
89 parent_div = grandparent_rate / parent_rate;
/linux-master/drivers/clk/bcm/
H A Dclk-iproc-asiu.c69 unsigned long parent_rate)
76 if (parent_rate == 0) {
84 clk->rate = parent_rate;
85 return parent_rate;
94 clk->rate = parent_rate / (div_h + div_l);
96 __func__, clk->rate, parent_rate, div_h, div_l);
102 unsigned long *parent_rate)
106 if (rate == 0 || *parent_rate == 0)
109 if (rate == *parent_rate)
110 return *parent_rate;
68 iproc_asiu_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) argument
101 iproc_asiu_clk_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *parent_rate) argument
119 iproc_asiu_clk_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) argument
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/linux-master/drivers/clk/sunxi/
H A Dclk-sun6i-ar100.c23 * rate = (parent_rate >> p) / (m + 1);
31 if (req->rate > req->parent_rate)
32 req->rate = req->parent_rate;
34 div = DIV_ROUND_UP(req->parent_rate, req->rate);
50 req->rate = (req->parent_rate >> shift) / div;
H A Dclk-sun9i-cpus.c50 unsigned long parent_rate)
61 parent_rate /= SUN9I_CPUS_PLL4_DIV_GET(reg) + 1;
64 rate = parent_rate / (SUN9I_CPUS_DIV_GET(reg) + 1);
70 u8 parent, unsigned long parent_rate)
78 if (parent_rate && rate > parent_rate)
79 rate = parent_rate;
81 div = DIV_ROUND_UP(parent_rate, rate);
107 return parent_rate / pre_div / div;
115 unsigned long parent_rate, bes local
49 sun9i_a80_cpus_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) argument
69 sun9i_a80_cpus_clk_round(unsigned long rate, u8 *divp, u8 *pre_divp, u8 parent, unsigned long parent_rate) argument
149 sun9i_a80_cpus_clk_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) argument
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