clk/analogbits/wrpll-cln28hpc.c

178  * @parent_rate: PLL input refclk rate (pre-R-divider)
189 				      unsigned long parent_rate)
193 	if (parent_rate > MAX_INPUT_FREQ || parent_rate < MIN_POST_DIVR_FREQ)
196 	c->parent_rate = parent_rate;
197 	max_r_for_parent = div_u64(parent_rate, MIN_POST_DIVR_FREQ);
200 	c->init_r = DIV_ROUND_UP_ULL(parent_rate, MAX_POST_DIVR_FREQ);
209  * @parent_rate: PLL input refclk rate (pre-R-divider)
227 			     unsigned long parent_rate)
241 	if (parent_rate != c->parent_rate) {
242 		if (__wrpll_update_parent_rate(c, parent_rate)) {
252 	if (target_rate == parent_rate) {
266 	ratio = div64_u64((target_vco_rate << ROUND_SHIFT), parent_rate);
282 		post_divr_freq = div_u64(parent_rate, r);
306 	post_divr_freq = div_u64(parent_rate, best_r);
321  * @parent_rate: PLL refclk rate
324  * PLL's input reference clock rate @parent_rate (before the R
337 				     unsigned long parent_rate)
348 	n = parent_rate * fbdiv * (c->divf + 1);