Searched refs:out_clks (Results 1 - 3 of 3) sorted by relevance

/linux-master/drivers/gpu/drm/amd/display/dc/dml2/
H A Ddml2_utils.h41 void dml2_copy_clocks_to_dc_state(struct dml2_dcn_clocks *out_clks, struct dc_state *context);
H A Ddml2_wrapper.c570 struct dml2_dcn_clocks out_clks; local
616 out_clks.dispclk_khz = (unsigned int)dml2->v20.dml_core_ctx.mp.Dispclk_calculated * 1000;
617 out_clks.p_state_supported = s->mode_support_info.DRAMClockChangeSupport[0] != dml_dram_clock_change_unsupported;
621 out_clks.dispclk_khz = (unsigned int)dml2->v20.dml_core_ctx.states.state_array[lowest_state_idx].dispclk_mhz * 1000;
624 out_clks.dcfclk_khz = (unsigned int)dml2->v20.dml_core_ctx.states.state_array[lowest_state_idx].dcfclk_mhz * 1000;
625 out_clks.fclk_khz = (unsigned int)dml2->v20.dml_core_ctx.states.state_array[lowest_state_idx].fabricclk_mhz * 1000;
626 out_clks.uclk_mts = (unsigned int)dml2->v20.dml_core_ctx.states.state_array[lowest_state_idx].dram_speed_mts;
627 out_clks.phyclk_khz = (unsigned int)dml2->v20.dml_core_ctx.states.state_array[lowest_state_idx].phyclk_mhz * 1000;
628 out_clks.socclk_khz = (unsigned int)dml2->v20.dml_core_ctx.states.state_array[lowest_state_idx].socclk_mhz * 1000;
629 out_clks
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H A Ddml2_utils.c190 void dml2_copy_clocks_to_dc_state(struct dml2_dcn_clocks *out_clks, struct dc_state *context) argument
192 context->bw_ctx.bw.dcn.clk.dispclk_khz = out_clks->dispclk_khz;
193 context->bw_ctx.bw.dcn.clk.dcfclk_khz = out_clks->dcfclk_khz;
194 context->bw_ctx.bw.dcn.clk.dramclk_khz = out_clks->uclk_mts / 16;
195 context->bw_ctx.bw.dcn.clk.fclk_khz = out_clks->fclk_khz;
196 context->bw_ctx.bw.dcn.clk.phyclk_khz = out_clks->phyclk_khz;
197 context->bw_ctx.bw.dcn.clk.socclk_khz = out_clks->socclk_khz;
198 context->bw_ctx.bw.dcn.clk.ref_dtbclk_khz = out_clks->ref_dtbclk_khz;
199 context->bw_ctx.bw.dcn.clk.p_state_change_support = out_clks->p_state_supported;

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