Searched refs:orr (Results 1 - 25 of 132) sorted by last modified time

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/linux-master/arch/arm/mm/
H A Dtlb-v7.S46 orr r0, r3, r0, lsl #PAGE_SHIFT @ Create initial MVA
H A Dtlb-v6.S44 orr r0, r3, r0, lsl #PAGE_SHIFT @ Create initial MVA
H A Dproc-xscale.S501 orr r2, r2, ip
548 orr r0, r0, #1 << 13 @ Its undefined whether this
555 orr r0, r0, r6
H A Dproc-v7.S172 ALT_SMP(orr r1, r1, #TTB_FLAGS_SMP)
173 ALT_UP(orr r1, r1, #TTB_FLAGS_UP)
310 orr r10, r10, #(1 << 6) @ Enable SMP/nAMP mode
313 orr r10, r10, r0 @ Set required bits
394 orr r10, r10, #1 << 12 @ set bit #12
399 orr r10, r10, #1 << 1 @ set bit #1
404 orr r10, r10, #1 << 24 @ set bit #24
409 orr r10, r10, #3 << 10 @ set bits #10 and #11
429 orr r10, r10, #3 << 10 @ set bits #10 and #11
461 orr r
[all...]
H A Dproc-xsc3.S68 orr \rd, \rd, #0x00e0
372 orr r0, r0, #0x18 @ cache the page table in L2
411 orr r2, r2, ip
447 orr r1, r1, #0x18 @ cache the page table in L2
463 orr r4, r4, #0x18 @ cache the page table in L2
471 orr r0, r0, #(1 << 10) @ enable L2 for LLR cache
485 orr r0, r0, r6 @ ..VI Z..S .... .C.M (mmu)
H A Dproc-v7m.S118 orr r5, #(V7M_SCB_SHCSR_USGFAULTENA | V7M_SCB_SHCSR_BUSFAULTENA | V7M_SCB_SHCSR_MEMFAULTENA)
140 orr r10, lr, #EXC_RET_THREADMODE_PROCESSSTACK
159 orr r0, #V7M_SCB_CCR_STKALIGN
160 orr r0, r0, r8
H A Dproc-v6.S107 ALT_SMP(orr r0, r0, #TTB_FLAGS_SMP)
108 ALT_UP(orr r0, r0, #TTB_FLAGS_UP)
116 orr r1, r1, r2 @ insert into new context ID
171 ALT_SMP(orr r1, r1, #TTB_FLAGS_SMP)
172 ALT_UP(orr r1, r1, #TTB_FLAGS_UP)
208 orr r0, r0, #0x20
220 ALT_SMP(orr r4, r4, #TTB_FLAGS_SMP)
221 ALT_UP(orr r4, r4, #TTB_FLAGS_UP)
222 ALT_SMP(orr r8, r8, #TTB_FLAGS_SMP)
223 ALT_UP(orr r
[all...]
H A Dproc-v7-3level.S49 orr rpgdh, rpgdh, r2, lsl #(48 - 32) @ upper 32-bits of pgd
121 ALT_SMP(orr \tmp, \tmp, #TTB_FLAGS_SMP)
122 ALT_UP(orr \tmp, \tmp, #TTB_FLAGS_UP)
123 ALT_SMP(orr \tmp, \tmp, #TTB_FLAGS_SMP << 16)
124 ALT_UP(orr \tmp, \tmp, #TTB_FLAGS_UP << 16)
H A Dproc-v7-2level.S46 ALT_SMP(orr r0, r0, #TTB_FLAGS_SMP)
47 ALT_UP(orr r0, r0, #TTB_FLAGS_UP)
80 orr r3, r3, r2
81 orr r3, r3, #PTE_EXT_AP0 | 2
148 ALT_SMP(orr \ttbr0l, \ttbr0l, #TTB_FLAGS_SMP)
149 ALT_UP(orr \ttbr0l, \ttbr0l, #TTB_FLAGS_UP)
150 ALT_SMP(orr \ttbr1, \ttbr1, #TTB_FLAGS_SMP)
151 ALT_UP(orr \ttbr1, \ttbr1, #TTB_FLAGS_UP)
H A Dproc-macros.S158 orr r3, r3, r2
159 orr r3, r3, #PTE_EXT_AP0 | 2
213 orr r2, r2, #PTE_TYPE_SMALL
255 orr r2, r2, #PTE_TYPE_EXT @ extended page
352 orr \dest, \addr, \dest, lsl #1 @ mask in the region size
353 orr \dest, \dest, \enable
H A Dproc-mohawk.S326 orr r0, r0, #0x18 @ cache the page table in L2
375 orr r1, r1, #0x18 @ cache the page table in L2
389 orr r4, r4, #0x18 @ cache the page table in L2
399 orr r0, r0, r6
H A Dproc-sa1100.S217 orr r0, r0, r6
H A Dproc-sa110.S179 orr r0, r0, r6
H A Dproc-feroceon.S155 1: orr ip, r1, r3
264 orr r3, r2, #PSR_I_BIT
311 orr r3, r2, #PSR_I_BIT
343 orr r3, r2, #PSR_I_BIT
375 orr r3, r2, #PSR_I_BIT
536 orr r0, r0, r6
H A Dproc-fa526.S165 orr r0, r0, r5
H A Dproc-arm926.S97 orr ip, r3, #PSR_F_BIT @ is disabled
442 orr r0, r0, r6
444 orr r0, r0, #0x4000 @ .1.. .... .... ....
H A Dproc-arm946.S112 1: orr r3, r1, #(CACHE_DENTRIES - 1) << 4 @ n entries
380 orr r0, r0, #0x00000200
385 orr r0, r0, #0x00001000 @ I-cache
386 orr r0, r0, #0x00000005 @ MPU/D-cache
388 orr r0, r0, #0x00004000 @ .1.. .... .... ....
H A Dproc-arm940.S118 1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
173 1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
196 1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
219 1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
242 1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
332 orr r0, r0, #0x00001000 @ I-cache
333 orr r0, r0, #0x00000005 @ MPU/D-cache
H A Dproc-arm925.S104 orr ip, ip, #0x00fe0000
105 orr ip, ip, #0x0000ce00
440 orr r0,r0,#1 << 1 @ transparent mode on
459 orr r0, r0, r6
461 orr r0, r0, #0x4000 @ .1.. .... .... ....
H A Dproc-arm920.S133 1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
350 1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
419 orr r0, r0, r6
H A Dproc-arm922.S135 1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
353 1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
396 orr r0, r0, r6
H A Dproc-arm740.S91 orr r0, r0, r4, lsl #1 @ the area register value
92 orr r0, r0, #1 @ set enable bit
104 orr r0, r0, r4, lsl #1 @ the area register value
105 orr r0, r0, #1 @ set enable bit
124 orr r0, r0, #0x0000000d @ MPU/Cache/WB
H A Dproc-arm1026.S421 orr r0, r0, r6
423 orr r0, r0, #0x4000 @ .R.. .... .... ....
H A Dproc-arm720.S125 orr r0, r0, r5
153 orr r0, r0, r6
H A Dproc-arm1020.S147 1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
397 orr ip, ip, r1, LSL #5 @ shift in/up index
452 orr r0, r0, r6
454 orr r0, r0, #0x4000 @ .R.. .... .... ....

Completed in 208 milliseconds

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