/linux-master/arch/arm/mm/ |
H A D | tlb-v7.S | 46 orr r0, r3, r0, lsl #PAGE_SHIFT @ Create initial MVA
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H A D | tlb-v6.S | 44 orr r0, r3, r0, lsl #PAGE_SHIFT @ Create initial MVA
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H A D | proc-xscale.S | 501 orr r2, r2, ip 548 orr r0, r0, #1 << 13 @ Its undefined whether this 555 orr r0, r0, r6
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H A D | proc-v7.S | 172 ALT_SMP(orr r1, r1, #TTB_FLAGS_SMP) 173 ALT_UP(orr r1, r1, #TTB_FLAGS_UP) 310 orr r10, r10, #(1 << 6) @ Enable SMP/nAMP mode 313 orr r10, r10, r0 @ Set required bits 394 orr r10, r10, #1 << 12 @ set bit #12 399 orr r10, r10, #1 << 1 @ set bit #1 404 orr r10, r10, #1 << 24 @ set bit #24 409 orr r10, r10, #3 << 10 @ set bits #10 and #11 429 orr r10, r10, #3 << 10 @ set bits #10 and #11 461 orr r [all...] |
H A D | proc-xsc3.S | 68 orr \rd, \rd, #0x00e0 372 orr r0, r0, #0x18 @ cache the page table in L2 411 orr r2, r2, ip 447 orr r1, r1, #0x18 @ cache the page table in L2 463 orr r4, r4, #0x18 @ cache the page table in L2 471 orr r0, r0, #(1 << 10) @ enable L2 for LLR cache 485 orr r0, r0, r6 @ ..VI Z..S .... .C.M (mmu)
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H A D | proc-v7m.S | 118 orr r5, #(V7M_SCB_SHCSR_USGFAULTENA | V7M_SCB_SHCSR_BUSFAULTENA | V7M_SCB_SHCSR_MEMFAULTENA) 140 orr r10, lr, #EXC_RET_THREADMODE_PROCESSSTACK 159 orr r0, #V7M_SCB_CCR_STKALIGN 160 orr r0, r0, r8
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H A D | proc-v6.S | 107 ALT_SMP(orr r0, r0, #TTB_FLAGS_SMP) 108 ALT_UP(orr r0, r0, #TTB_FLAGS_UP) 116 orr r1, r1, r2 @ insert into new context ID 171 ALT_SMP(orr r1, r1, #TTB_FLAGS_SMP) 172 ALT_UP(orr r1, r1, #TTB_FLAGS_UP) 208 orr r0, r0, #0x20 220 ALT_SMP(orr r4, r4, #TTB_FLAGS_SMP) 221 ALT_UP(orr r4, r4, #TTB_FLAGS_UP) 222 ALT_SMP(orr r8, r8, #TTB_FLAGS_SMP) 223 ALT_UP(orr r [all...] |
H A D | proc-v7-3level.S | 49 orr rpgdh, rpgdh, r2, lsl #(48 - 32) @ upper 32-bits of pgd 121 ALT_SMP(orr \tmp, \tmp, #TTB_FLAGS_SMP) 122 ALT_UP(orr \tmp, \tmp, #TTB_FLAGS_UP) 123 ALT_SMP(orr \tmp, \tmp, #TTB_FLAGS_SMP << 16) 124 ALT_UP(orr \tmp, \tmp, #TTB_FLAGS_UP << 16)
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H A D | proc-v7-2level.S | 46 ALT_SMP(orr r0, r0, #TTB_FLAGS_SMP) 47 ALT_UP(orr r0, r0, #TTB_FLAGS_UP) 80 orr r3, r3, r2 81 orr r3, r3, #PTE_EXT_AP0 | 2 148 ALT_SMP(orr \ttbr0l, \ttbr0l, #TTB_FLAGS_SMP) 149 ALT_UP(orr \ttbr0l, \ttbr0l, #TTB_FLAGS_UP) 150 ALT_SMP(orr \ttbr1, \ttbr1, #TTB_FLAGS_SMP) 151 ALT_UP(orr \ttbr1, \ttbr1, #TTB_FLAGS_UP)
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H A D | proc-macros.S | 158 orr r3, r3, r2 159 orr r3, r3, #PTE_EXT_AP0 | 2 213 orr r2, r2, #PTE_TYPE_SMALL 255 orr r2, r2, #PTE_TYPE_EXT @ extended page 352 orr \dest, \addr, \dest, lsl #1 @ mask in the region size 353 orr \dest, \dest, \enable
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H A D | proc-mohawk.S | 326 orr r0, r0, #0x18 @ cache the page table in L2 375 orr r1, r1, #0x18 @ cache the page table in L2 389 orr r4, r4, #0x18 @ cache the page table in L2 399 orr r0, r0, r6
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H A D | proc-sa1100.S | 217 orr r0, r0, r6
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H A D | proc-sa110.S | 179 orr r0, r0, r6
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H A D | proc-feroceon.S | 155 1: orr ip, r1, r3 264 orr r3, r2, #PSR_I_BIT 311 orr r3, r2, #PSR_I_BIT 343 orr r3, r2, #PSR_I_BIT 375 orr r3, r2, #PSR_I_BIT 536 orr r0, r0, r6
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H A D | proc-fa526.S | 165 orr r0, r0, r5
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H A D | proc-arm926.S | 97 orr ip, r3, #PSR_F_BIT @ is disabled 442 orr r0, r0, r6 444 orr r0, r0, #0x4000 @ .1.. .... .... ....
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H A D | proc-arm946.S | 112 1: orr r3, r1, #(CACHE_DENTRIES - 1) << 4 @ n entries 380 orr r0, r0, #0x00000200 385 orr r0, r0, #0x00001000 @ I-cache 386 orr r0, r0, #0x00000005 @ MPU/D-cache 388 orr r0, r0, #0x00004000 @ .1.. .... .... ....
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H A D | proc-arm940.S | 118 1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries 173 1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries 196 1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries 219 1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries 242 1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries 332 orr r0, r0, #0x00001000 @ I-cache 333 orr r0, r0, #0x00000005 @ MPU/D-cache
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H A D | proc-arm925.S | 104 orr ip, ip, #0x00fe0000 105 orr ip, ip, #0x0000ce00 440 orr r0,r0,#1 << 1 @ transparent mode on 459 orr r0, r0, r6 461 orr r0, r0, #0x4000 @ .1.. .... .... ....
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H A D | proc-arm920.S | 133 1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries 350 1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries 419 orr r0, r0, r6
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H A D | proc-arm922.S | 135 1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries 353 1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries 396 orr r0, r0, r6
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H A D | proc-arm740.S | 91 orr r0, r0, r4, lsl #1 @ the area register value 92 orr r0, r0, #1 @ set enable bit 104 orr r0, r0, r4, lsl #1 @ the area register value 105 orr r0, r0, #1 @ set enable bit 124 orr r0, r0, #0x0000000d @ MPU/Cache/WB
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H A D | proc-arm1026.S | 421 orr r0, r0, r6 423 orr r0, r0, #0x4000 @ .R.. .... .... ....
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H A D | proc-arm720.S | 125 orr r0, r0, r5 153 orr r0, r0, r6
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H A D | proc-arm1020.S | 147 1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries 397 orr ip, ip, r1, LSL #5 @ shift in/up index 452 orr r0, r0, r6 454 orr r0, r0, #0x4000 @ .R.. .... .... ....
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