/linux-master/drivers/gpu/drm/sti/ |
H A D | sti_hdmi_tx3g4c28phy.c | 48 uint32_t odf; member in struct:plldividers_s 79 u32 val, tmdsck, idf, odf, pllctrl = 0; local 89 odf = plldividers[i].odf; 111 pllctrl |= odf << PLL_CFG_ODF_SHIFT;
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/linux-master/drivers/gpu/drm/stm/ |
H A D | dw_mipi_dsi-stm.c | 130 static int dsi_pll_get_clkout_khz(int clkin_khz, int idf, int ndiv, int odf) argument 132 int divisor = idf * odf; 143 int *idf, int *ndiv, int *odf) 185 *odf = o; 246 unsigned int idf, ndiv, odf, pll_in_khz, pll_out_khz; local 272 odf = 0; 274 &idf, &ndiv, &odf); 279 pll_out_khz = dsi_pll_get_clkout_khz(pll_in_khz, idf, ndiv, odf); 283 (ndiv << 2) | (idf << 11) | ((ffs(odf) - 1) << 16)); 333 unsigned int idf, ndiv, odf, pll_in_kh local 141 dsi_pll_get_params(struct dw_mipi_dsi_stm *dsi, int clkin_khz, int clkout_khz, int *idf, int *ndiv, int *odf) argument [all...] |
/linux-master/drivers/clk/st/ |
H A D | clkgen-pll.c | 52 struct clkgen_field odf[C32_MAX_ODFS]; member in struct:clkgen_pll_data 83 .odf = { CLKGEN_FIELD(0x2b4, C32_ODF_MASK, 0) }, 93 { .name = "clk-s-a0-pll-odf-0", }, 102 { .name = "clk-s-c0-pll0-odf-0", }, 118 .odf = { CLKGEN_FIELD(0x2dc, C32_ODF_MASK, 0) }, 128 { .name = "clk-s-c0-pll1-odf-0", }, 144 .odf = { CLKGEN_FIELD(0x1b0, C32_ODF_MASK, 8) }, 154 { .name = "clockgen-a9-pll-odf", }, 170 .odf = { CLKGEN_FIELD(0x1b0, C28_ODF_MASK, 8) }, 179 { .name = "clockgen-a9-pll-odf", }, 222 unsigned long odf; member in struct:stm_pll 699 clkgen_odf_register(const char *parent_name, void __iomem *reg, struct clkgen_pll_data *pll_data, unsigned long pll_flags, int odf, spinlock_t *odf_lock, const char *odf_name) argument 756 int num_odfs, odf; local [all...] |
/linux-master/drivers/clk/ |
H A D | clk-stm32h7.c | 1306 int odf; local 1315 for (odf = 0; odf < 3; odf++) { 1316 int idx = n * 3 + odf; 1318 get_cfg_composite_div(&odf_clk_gcfg, &stm32_odf[n][odf], 1322 stm32_odf[n][odf].name, 1323 stm32_odf[n][odf].parent_name, 1324 stm32_odf[n][odf].num_parents, 1328 stm32_odf[n][odf] [all...] |
/linux-master/drivers/media/dvb-frontends/ |
H A D | stv0910.c | 795 u32 odf = 4; local 798 u32 ndiv = (fphi * odf * idf) / quartz; 846 write_reg(state, RSTV0910_NCOARSE2, odf); 850 state->base->mclk = fvco / (2 * odf) * 1000000;
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