Searched refs:nv_funcs (Results 1 - 5 of 5) sorted by relevance

/linux-master/drivers/gpu/drm/amd/display/amdgpu_dm/
H A Damdgpu_dm_pp_smu.c775 funcs->nv_funcs.pp_smu.dm = ctx;
776 funcs->nv_funcs.set_display_count = pp_nv_set_display_count;
777 funcs->nv_funcs.set_hard_min_dcfclk_by_freq =
779 funcs->nv_funcs.set_min_deep_sleep_dcfclk =
781 funcs->nv_funcs.set_voltage_by_freq =
783 funcs->nv_funcs.set_wm_ranges = pp_nv_set_wm_ranges;
786 funcs->nv_funcs.set_pme_wa_enable = NULL;
788 funcs->nv_funcs.set_hard_min_uclk_by_freq = pp_nv_set_hard_min_uclk_by_freq;
790 funcs->nv_funcs.get_maximum_sustainable_clocks = pp_nv_get_maximum_sustainable_clocks;
792 funcs->nv_funcs
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/
H A Ddm_pp_smu.h314 struct pp_smu_funcs_nv nv_funcs; member in union:pp_smu_funcs::__anon230
/linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/
H A Ddcn20_clk_mgr.c248 pp_smu = &dc->res_pool->pp_smu->nv_funcs;
417 pp_smu = &clk_mgr->pp_smu->nv_funcs;
499 if (!clk_mgr->pp_smu || !clk_mgr->pp_smu->nv_funcs.set_voltage_by_freq)
502 pp_smu = &clk_mgr->pp_smu->nv_funcs;
/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn20/
H A Ddcn20_resource.c2374 if (pool->base.pp_smu->nv_funcs.get_uclk_dpm_states) {
2375 status = (pool->base.pp_smu->nv_funcs.get_uclk_dpm_states)
2376 (&pool->base.pp_smu->nv_funcs.pp_smu, uclk_states, &num_states);
2381 if (pool->base.pp_smu->nv_funcs.get_maximum_sustainable_clocks) {
2382 status = (*pool->base.pp_smu->nv_funcs.get_maximum_sustainable_clocks)
2383 (&pool->base.pp_smu->nv_funcs.pp_smu, &max_clocks);
2625 if (pool->base.pp_smu->nv_funcs.set_wm_ranges)
2626 pool->base.pp_smu->nv_funcs.set_wm_ranges(&pool->base.pp_smu->nv_funcs.pp_smu, &ranges);
/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn301/
H A Ddcn301_resource.c1363 pp_smu->nv_funcs.set_wm_ranges(&pp_smu->nv_funcs.pp_smu, &ranges);
1549 if (!dc->debug.disable_pplib_wm_range && pool->base.pp_smu->nv_funcs.set_wm_ranges)

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