Searched refs:nv04_display (Results 1 - 11 of 11) sorted by relevance

/linux-master/drivers/gpu/drm/nouveau/dispnv04/
H A Ddisp.c60 struct nv04_display *disp = nv04_display(dev);
101 struct nv04_display *disp = nv04_display(dev);
191 struct nv04_display *disp = nv04_display(dev);
223 struct nv04_display *disp;
H A Ddisp.h83 struct nv04_display { struct
93 static inline struct nv04_display *
94 nv04_display(struct drm_device *dev) function
99 /* nv04_display.c */
H A Dcrtc.c67 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];
82 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];
124 struct nv04_mode_state *state = &nv04_display(dev)->mode_reg;
241 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];
466 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];
467 struct nv04_crtc_reg *savep = &nv04_display(dev)->saved_reg.crtc_reg[nv_crtc->index];
546 regp->CRTC[NV_CIO_CRE_TVOUT_LATENCY] = nv04_display(dev)->saved_reg.crtc_reg[0].CRTC[NV_CIO_CRE_TVOUT_LATENCY];
612 struct nv04_display *disp = nv04_display(crtc->dev);
659 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, nv04_display(de
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H A Ddfp.c95 struct nv04_crtc_reg *crtcstate = nv04_display(dev)->mode_reg.crtc_reg;
122 fpc = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index].fp_control;
137 fpc = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index].fp_control;
207 struct nv04_mode_state *state = &nv04_display(dev)->mode_reg;
237 if (nv_encoder->dcb->type == DCB_OUTPUT_LVDS && nv04_display(dev)->saved_reg.sel_clk & 0xf0) {
238 int shift = (nv04_display(dev)->saved_reg.sel_clk & 0x50) ? 0 : 1;
251 struct nv04_crtc_reg *crtcstate = nv04_display(dev)->mode_reg.crtc_reg;
288 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];
289 struct nv04_crtc_reg *savep = &nv04_display(dev)->saved_reg.crtc_reg[nv_crtc->index];
464 nv04_display(de
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H A Dcursor.c42 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];
H A Dtvnv04.c79 struct nv04_mode_state *state = &nv04_display(dev)->mode_reg;
107 struct nv04_crtc_reg *state = &nv04_display(dev)->mode_reg.crtc_reg[head];
146 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];
H A Ddac.c432 uint32_t *dac_users = &nv04_display(dev)->dac_users[ffs(dcb->or) - 1];
457 (nv04_display(dev)->dac_users[ffs(dcb->or) - 1] & ~(1 << dcb->index));
H A Dhw.h376 &nv04_display(dev)->mode_reg.crtc_reg[head].CRTC[NV_CIO_CRE_HCUR_ADDR1_INDEX];
H A Dtvnv17.c404 uint8_t *cr_lcd = &nv04_display(dev)->mode_reg.crtc_reg[head].CRTC[
465 struct nv04_crtc_reg *regs = &nv04_display(dev)->mode_reg.crtc_reg[head];
H A Dhw.c300 nv04_display(dev)->saved_vga_font[plane][i] =
303 iowrite32_native(nv04_display(dev)->saved_vga_font[plane][i],
H A Dtvmodesnv17.c546 struct nv04_crtc_reg *regs = &nv04_display(dev)->mode_reg.crtc_reg[head];

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