/linux-master/drivers/gpu/drm/amd/display/dc/dcn32/ |
H A D | dcn32_mpc.c | 48 int mpcc_id; local 54 for (mpcc_id = 0; mpcc_id < mpc30->num_mpcc; mpcc_id++) { 55 REG_UPDATE(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_SHAPER_MEM_LOW_PWR_MODE, 3); 56 REG_UPDATE(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_3DLUT_MEM_LOW_PWR_MODE, 3); 57 REG_UPDATE(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_1DLUT_MEM_LOW_PWR_MODE, 3); 61 for (mpcc_id = 0; mpcc_id < mpc30->num_mpcc; mpcc_id 67 mpc32_power_on_blnd_lut( struct mpc *mpc, uint32_t mpcc_id, bool power_on) argument 92 mpc32_get_post1dlut_current(struct mpc *mpc, uint32_t mpcc_id) argument 124 mpc32_configure_post1dlut( struct mpc *mpc, uint32_t mpcc_id, bool is_ram_a) argument 167 mpc32_program_post1dluta_settings( struct mpc *mpc, uint32_t mpcc_id, const struct pwl_params *params) argument 196 mpc32_program_post1dlutb_settings( struct mpc *mpc, uint32_t mpcc_id, const struct pwl_params *params) argument 224 mpc32_program_post1dlut_pwl( struct mpc *mpc, uint32_t mpcc_id, const struct pwl_result_data *rgb, uint32_t num) argument 261 mpc32_program_post1dlut( struct mpc *mpc, const struct pwl_params *params, uint32_t mpcc_id) argument 301 mpc32_get_shaper_current(struct mpc *mpc, uint32_t mpcc_id) argument 328 mpc32_configure_shaper_lut( struct mpc *mpc, bool is_ram_a, uint32_t mpcc_id) argument 343 mpc32_program_shaper_luta_settings( struct mpc *mpc, const struct pwl_params *params, uint32_t mpcc_id) argument 493 mpc32_program_shaper_lutb_settings( struct mpc *mpc, const struct pwl_params *params, uint32_t mpcc_id) argument 644 mpc32_program_shaper_lut( struct mpc *mpc, const struct pwl_result_data *rgb, uint32_t num, uint32_t mpcc_id) argument 678 mpc32_power_on_shaper_3dlut( struct mpc *mpc, uint32_t mpcc_id, bool power_on) argument 708 mpc32_program_shaper( struct mpc *mpc, const struct pwl_params *params, uint32_t mpcc_id) argument 750 get3dlut_config( struct mpc *mpc, bool *is_17x17x17, bool *is_12bits_color_channel, int mpcc_id) argument 796 mpc32_select_3dlut_ram( struct mpc *mpc, enum dc_lut_mode mode, bool is_color_channel_12bits, uint32_t mpcc_id) argument 810 mpc32_select_3dlut_ram_mask( struct mpc *mpc, uint32_t ram_selection_mask, uint32_t mpcc_id) argument 823 mpc32_set3dlut_ram12( struct mpc *mpc, const struct dc_rgb *lut, uint32_t entries, uint32_t mpcc_id) argument 855 mpc32_set3dlut_ram10( struct mpc *mpc, const struct dc_rgb *lut, uint32_t entries, uint32_t mpcc_id) argument 877 mpc32_set_3dlut_mode( struct mpc *mpc, enum dc_lut_mode mode, bool is_color_channel_12bits, bool is_lut_size17x17x17, uint32_t mpcc_id) argument 904 mpc32_program_3dlut( struct mpc *mpc, const struct tetrahedral_params *params, int mpcc_id) argument [all...] |
H A D | dcn32_mpc.h | 315 int mpcc_id); 319 uint32_t mpcc_id); 323 uint32_t mpcc_id); 335 uint32_t mpcc_id, 339 uint32_t mpcc_id, 344 uint32_t mpcc_id, 348 uint32_t mpcc_id, 352 uint32_t mpcc_id, 358 uint32_t mpcc_id); 362 uint32_t mpcc_id); [all...] |
H A D | dcn32_hubp.c | 222 hubp2->base.mpcc_id = 0xf;
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/linux-master/drivers/gpu/drm/amd/display/dc/dcn10/ |
H A D | dcn10_mpc.c | 42 int mpcc_id) 45 struct mpcc *bottommost_mpcc = mpc1_get_mpcc(mpc, mpcc_id); 68 REG_SET(MPCC_BG_R_CR[bottommost_mpcc->mpcc_id], 0, 70 REG_SET(MPCC_BG_G_Y[bottommost_mpcc->mpcc_id], 0, 72 REG_SET(MPCC_BG_B_CB[bottommost_mpcc->mpcc_id], 0, 79 int mpcc_id) 82 struct mpcc *mpcc = mpc1_get_mpcc(mpc, mpcc_id); 84 REG_UPDATE_5(MPCC_CONTROL[mpcc_id], 97 int mpcc_id) 101 REG_UPDATE_6(MPCC_SM_CONTROL[mpcc_id], 40 mpc1_set_bg_color(struct mpc *mpc, struct tg_color *bg_color, int mpcc_id) argument 76 mpc1_update_blending( struct mpc *mpc, struct mpcc_blnd_cfg *blnd_cfg, int mpcc_id) argument 94 mpc1_update_stereo_mix( struct mpc *mpc, struct mpcc_sm_cfg *sm_cfg, int mpcc_id) argument 119 mpc1_get_mpcc(struct mpc *mpc, int mpcc_id) argument 145 mpc1_is_mpcc_idle(struct mpc *mpc, int mpcc_id) argument 161 mpc1_assert_mpcc_idle_before_connect(struct mpc *mpc, int mpcc_id) argument 195 mpc1_insert_plane( struct mpc *mpc, struct mpc_tree *tree, struct mpcc_blnd_cfg *blnd_cfg, struct mpcc_sm_cfg *sm_cfg, struct mpcc *insert_above_mpcc, int dpp_id, int mpcc_id) argument 294 int mpcc_id = mpcc_to_remove->mpcc_id; local 374 int mpcc_id; local 393 mpc1_mpc_init_single_inst(struct mpc *mpc, unsigned int mpcc_id) argument 422 int mpcc_id; local [all...] |
H A D | dcn10_mpc.h | 148 int mpcc_id); 160 unsigned int mpcc_id); 174 int mpcc_id); 178 int mpcc_id); 182 int mpcc_id); 190 int mpcc_id);
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/linux-master/drivers/gpu/drm/amd/display/dc/dcn20/ |
H A D | dcn20_mpc.c | 51 int mpcc_id) 55 struct mpcc *mpcc = mpc1_get_mpcc(mpc, mpcc_id); 57 REG_UPDATE_7(MPCC_CONTROL[mpcc_id], 66 REG_SET(MPCC_TOP_GAIN[mpcc_id], 0, MPCC_TOP_GAIN, blnd_cfg->top_gain); 67 REG_SET(MPCC_BOT_GAIN_INSIDE[mpcc_id], 0, MPCC_BOT_GAIN_INSIDE, blnd_cfg->bottom_inside_gain); 68 REG_SET(MPCC_BOT_GAIN_OUTSIDE[mpcc_id], 0, MPCC_BOT_GAIN_OUTSIDE, blnd_cfg->bottom_outside_gain); 273 struct mpc *mpc, int mpcc_id, 278 REG_SET(MPCC_MEM_PWR_CTRL[mpcc_id], 0, 284 struct mpc *mpc, int mpcc_id, 289 REG_UPDATE_2(MPCC_OGAM_LUT_RAM_CONTROL[mpcc_id], 48 mpc2_update_blending( struct mpc *mpc, struct mpcc_blnd_cfg *blnd_cfg, int mpcc_id) argument 272 mpc20_power_on_ogam_lut( struct mpc *mpc, int mpcc_id, bool power_on) argument 283 mpc20_configure_ogam_lut( struct mpc *mpc, int mpcc_id, bool is_ram_a) argument 296 mpc20_get_ogam_current(struct mpc *mpc, int mpcc_id) argument 322 mpc2_program_lutb(struct mpc *mpc, int mpcc_id, const struct pwl_params *params) argument 349 mpc2_program_luta(struct mpc *mpc, int mpcc_id, const struct pwl_params *params) argument 376 mpc20_program_ogam_pwl( struct mpc *mpc, int mpcc_id, const struct pwl_result_data *rgb, uint32_t num) argument 403 apply_DEDCN20_305_wa(struct mpc *mpc, int mpcc_id, enum dc_lut_mode current_mode, enum dc_lut_mode next_mode) argument 427 mpc2_set_output_gamma( struct mpc *mpc, int mpcc_id, const struct pwl_params *params) argument 483 mpc2_assert_mpcc_idle_before_connect(struct mpc *mpc, int mpcc_id) argument [all...] |
H A D | dcn20_mpc.h | 280 int mpcc_id); 306 int mpcc_id, 310 void mpc2_assert_mpcc_idle_before_connect(struct mpc *mpc, int mpcc_id); 311 void mpc20_power_on_ogam_lut(struct mpc *mpc, int mpcc_id, bool power_on);
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/linux-master/drivers/gpu/drm/amd/display/dc/inc/hw/ |
H A D | mpc.h | 204 * @mpcc_id: MPCC physical instance. 206 int mpcc_id; member in struct:mpcc 306 * - [in] mpcc_id - The MPCC physical instance to use for blending. 319 int mpcc_id); 357 unsigned int mpcc_id); 368 * - [in] mpcc_id - The MPCC physical instance. 377 int mpcc_id); 417 * - [in] mpcc_id - The MPCC physical instance to use for blending. 430 int mpcc_id); 462 void (*assert_mpcc_idle_before_connect)(struct mpc *mpc, int mpcc_id); [all...] |
H A D | hubp.h | 76 int mpcc_id; member in struct:hubp
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/linux-master/drivers/gpu/drm/amd/display/dc/dcn30/ |
H A D | dcn30_mpc.c | 62 void mpc3_mpc_init_single_inst(struct mpc *mpc, unsigned int mpcc_id) argument 66 mpc1_mpc_init_single_inst(mpc, mpcc_id); 71 if (mpcc_id < MAX_OPP && REG(MUX[mpcc_id])) 73 REG_UPDATE_2(MUX[mpcc_id], MPC_OUT_RATE_CONTROL_DISABLE, 95 int mpcc_id) 100 MPC_DWB0_MUX, mpcc_id); 113 enum dc_lut_mode mpc3_get_ogam_current(struct mpc *mpc, int mpcc_id) argument 123 REG_GET_2(MPCC_OGAM_CONTROL[mpcc_id], MPCC_OGAM_MODE_CURRENT, &state_mode, 152 struct mpc *mpc, int mpcc_id, 92 mpc3_set_dwb_mux( struct mpc *mpc, int dwb_id, int mpcc_id) argument 151 mpc3_power_on_ogam_lut( struct mpc *mpc, int mpcc_id, bool power_on) argument 171 mpc3_configure_ogam_lut( struct mpc *mpc, int mpcc_id, bool is_ram_a) argument 218 mpc3_program_luta(struct mpc *mpc, int mpcc_id, const struct pwl_params *params) argument 251 mpc3_program_lutb(struct mpc *mpc, int mpcc_id, const struct pwl_params *params) argument 285 mpc3_program_ogam_pwl( struct mpc *mpc, int mpcc_id, const struct pwl_result_data *rgb, uint32_t num) argument 324 mpc3_set_output_gamma( struct mpc *mpc, int mpcc_id, const struct pwl_params *params) argument 1049 program_gamut_remap( struct dcn30_mpc *mpc30, int mpcc_id, const uint16_t *regval, int select) argument 1108 mpc3_set_gamut_remap( struct mpc *mpc, int mpcc_id, const struct mpc_grph_gamut_adjustment *adjust) argument 1143 read_gamut_remap(struct dcn30_mpc *mpc30, int mpcc_id, uint16_t *regval, uint32_t *select) argument 1181 mpc3_get_gamut_remap(struct mpc *mpc, int mpcc_id, struct mpc_grph_gamut_adjustment *adjust) argument 1398 mpcc3_acquire_rmu(struct mpc *mpc, int mpcc_id, int rmu_idx) argument 1417 mpcc3_release_rmu(struct mpc *mpc, int mpcc_id) argument 1439 int mpcc_id; local [all...] |
H A D | dcn30_mpc.h | 1015 unsigned int mpcc_id); 1028 int mpcc_id, int rmu_idx); 1054 int mpcc_id, 1063 int mpcc_id, 1067 int mpcc_id, 1078 int mpcc_id); 1089 struct mpc *mpc, int mpcc_id, 1096 int mpcc_id);
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H A D | dcn30_hubp.c | 529 hubp2->base.mpcc_id = 0xf;
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/linux-master/drivers/gpu/drm/amd/display/dc/hwss/dcn201/ |
H A D | dcn201_hwseq.c | 313 hubp->mpcc_id = dpp->inst; 425 int mpcc_id, dpp_id; local 480 mpcc_id = dpp_id; 484 dc->hwss.update_visual_confirm_color(dc, pipe_ctx, mpcc_id); 485 mpc->funcs->update_blending(mpc, &blnd_cfg, mpcc_id); 506 dc->res_pool->mpc, mpcc_id); 509 dc->hwss.update_visual_confirm_color(dc, pipe_ctx, mpcc_id); 516 mpcc_id); 520 hubp->mpcc_id = mpcc_id; [all...] |
/linux-master/drivers/gpu/drm/amd/display/dc/dcn31/ |
H A D | dcn31_hubp.c | 116 hubp2->base.mpcc_id = 0xf;
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/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn30/ |
H A D | dcn30_resource.h | 86 int mpcc_id,
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/linux-master/drivers/gpu/drm/amd/display/dc/dcn201/ |
H A D | dcn201_mpc.c | 64 mpcc->mpcc_id = mpcc_inst;
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H A D | dcn201_hubp.c | 146 hubp201->base.mpcc_id = 0xf;
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/linux-master/drivers/gpu/drm/amd/display/dc/hwss/ |
H A D | hw_sequencer.h | 115 int mpcc_id; member in struct:update_visual_confirm_params 120 int mpcc_id; member in struct:power_on_mpc_mem_pwr_params 411 int mpcc_id);
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/linux-master/drivers/gpu/drm/amd/display/dc/dcn35/ |
H A D | dcn35_hubp.c | 236 hubp2->base.mpcc_id = 0xf;
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/linux-master/drivers/gpu/drm/amd/display/dc/hwss/dcn30/ |
H A D | dcn30_hwseq.c | 246 int mpcc_id = pipe_ctx->plane_res.hubp->inst; local 273 if (mpcc_id_projected != mpcc_id) 276 * mpcc_id into acquire_post_bldn_3dlut 278 acquired_rmu = mpc->funcs->acquire_rmu(mpc, mpcc_id, 288 // loop through the available mux and release the requested mpcc_id 289 mpc->funcs->release_rmu(mpc, mpcc_id); 343 int mpcc_id = pipe_ctx->plane_res.hubp->inst; local 372 mpc->funcs->set_gamut_remap(mpc, mpcc_id, &mpc_adjust); 379 int mpcc_id = pipe_ctx->plane_res.hubp->inst; local 403 mpc->funcs->set_output_gamma(mpc, mpcc_id, param [all...] |
/linux-master/drivers/gpu/drm/amd/display/dc/hwss/dcn32/ |
H A D | dcn32_hwseq.c | 439 int mpcc_id = pipe_ctx->plane_res.hubp->inst; local 461 mpcc_id); 465 mpcc_id); 475 int mpcc_id = pipe_ctx->plane_res.hubp->inst; local 490 result = mpc->funcs->program_1dlut(mpc, lut_params, mpcc_id); 506 result = mpc->funcs->program_shaper(mpc, lut_params, mpcc_id); 510 result = mpc->funcs->program_3dlut(mpc, &plane_state->lut3d_func->lut_3d, mpcc_id); 512 result = mpc->funcs->program_3dlut(mpc, NULL, mpcc_id); 563 int mpcc_id = pipe_ctx->plane_res.hubp->inst; local 587 mpc->funcs->set_output_gamma(mpc, mpcc_id, param [all...] |
/linux-master/drivers/gpu/drm/amd/display/dc/core/ |
H A D | dc_hw_sequencer.c | 667 block_sequence[*num_steps].params.power_on_mpc_mem_pwr_params.mpcc_id = current_mpc_pipe->plane_res.hubp->inst; 786 params->update_visual_confirm_params.mpcc_id); 860 int mpcc_id = params->power_on_mpc_mem_pwr_params.mpcc_id; local 864 mpc->funcs->power_on_mpc_mem_pwr(mpc, mpcc_id, power_on);
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/linux-master/drivers/gpu/drm/amd/display/dc/hwss/dcn10/ |
H A D | dcn10_hwseq.h | 208 int mpcc_id);
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H A D | dcn10_hwseq.c | 1464 hubp->mpcc_id = dpp->inst; 2660 int mpcc_id) 2666 mpc->funcs->set_bg_color(mpc, &(pipe_ctx->visual_confirm_color), mpcc_id); 2675 int mpcc_id; local 2714 mpcc_id = hubp->inst; 2718 mpc->funcs->update_blending(mpc, &blnd_cfg, mpcc_id); 2719 dc->hwss.update_visual_confirm_color(dc, pipe_ctx, mpcc_id); 2724 new_mpcc = mpc->funcs->get_mpcc_for_dpp(mpc_tree_params, mpcc_id); 2731 dc->res_pool->mpc, mpcc_id); 2740 mpcc_id); 2658 dcn10_update_visual_confirm_color(struct dc *dc, struct pipe_ctx *pipe_ctx, int mpcc_id) argument [all...] |
/linux-master/drivers/gpu/drm/amd/display/dc/hwss/dcn20/ |
H A D | dcn20_hwseq.c | 989 int mpcc_id = pipe_ctx->plane_res.hubp->inst; local 992 mpc->funcs->power_on_mpc_mem_pwr(mpc, mpcc_id, true); 1012 int mpcc_id = pipe_ctx->plane_res.hubp->inst; local 1023 mpc->funcs->power_on_mpc_mem_pwr(mpc, mpcc_id, true); 1043 mpc->funcs->set_output_gamma(mpc, mpcc_id, params); 2793 int mpcc_id; local 2837 mpcc_id = hubp->inst; 2842 mpc->funcs->update_blending(mpc, &blnd_cfg, mpcc_id); 2843 dc->hwss.update_visual_confirm_color(dc, pipe_ctx, mpcc_id); 2848 new_mpcc = mpc->funcs->get_mpcc_for_dpp(mpc_tree_params, mpcc_id); [all...] |