Searched refs:mmCGTS_CU3_TA_SQC_CTRL_REG_BASE_IDX (Results 1 - 3 of 3) sorted by path

/linux-master/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_offset.h6348 #define mmCGTS_CU3_TA_SQC_CTRL_REG_BASE_IDX 1 macro
H A Dgc_9_1_offset.h6570 #define mmCGTS_CU3_TA_SQC_CTRL_REG_BASE_IDX 1 macro
H A Dgc_9_2_1_offset.h6582 #define mmCGTS_CU3_TA_SQC_CTRL_REG_BASE_IDX 1 macro

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