Searched refs:mclk (Results 1 - 13 of 13) sorted by relevance

/freebsd-11-stable/sys/arm/at91/
H A Dat91_ohci.c72 struct at91_pmc_clock *mclk; member in struct:at91_ohci_softc
103 sc->mclk = at91_pmc_clock_ref("mck");
144 at91_pmc_clock_enable(sc->mclk);
187 at91_pmc_clock_disable(sc->mclk);
190 at91_pmc_clock_deref(sc->mclk);
H A Dat91_ohci_fdt.c76 struct at91_pmc_clock *mclk; member in struct:at91_ohci_softc
109 sc->mclk = at91_pmc_clock_ref("mck");
150 at91_pmc_clock_enable(sc->mclk);
194 at91_pmc_clock_disable(sc->mclk);
197 at91_pmc_clock_deref(sc->mclk);
/freebsd-11-stable/sys/dev/drm2/radeon/
H A Dradeon_pm.c164 u32 sclk, mclk; local
179 * mclk and vddci.
186 mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
187 clock_info[rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx].mclk;
189 mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
190 clock_info[rdev->pm.requested_clock_mode_index].mclk;
192 if (mclk > rdev->pm.default_mclk)
193 mclk = rdev->pm.default_mclk;
222 if (rdev->asic->pm.set_memory_clock && (mclk != rdev->pm.current_mclk)) {
224 radeon_set_memory_clock(rdev, mclk);
[all...]
H A Dradeon_atombios.c2060 rdev->pm.power_state[state_index].clock_info[0].mclk =
2065 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2095 rdev->pm.power_state[state_index].clock_info[0].mclk =
2100 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2131 rdev->pm.power_state[state_index].clock_info[0].mclk =
2136 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2331 rdev->pm.default_mclk = rdev->pm.power_state[state_index].clock_info[0].mclk;
2335 /* patch the table values with the default slck/mclk from firmware info */
2337 rdev->pm.power_state[state_index].clock_info[j].mclk =
2353 u32 sclk, mclk; local
[all...]
H A Dradeon_clocks.c73 uint32_t fb_div, ref_div, post_div, mclk; local
86 mclk = fb_div / ref_div;
90 mclk >>= 1;
92 mclk >>= 2;
94 mclk >>= 3;
96 return mclk;
H A Dradeon_device.c486 * Used when sclk/mclk are switched or display modes are set.
493 u32 mclk = rdev->pm.current_mclk; local
495 /* sclk/mclk in Mhz */
499 rdev->pm.mclk.full = dfixed_const(mclk);
500 rdev->pm.mclk.full = dfixed_div(rdev->pm.mclk, a);
H A Dradeon_combios.c825 uint16_t sclk, mclk; local
878 /* default sclk/mclk */
880 mclk = RBIOS16(pll_info + 0x8);
883 if (mclk == 0)
884 mclk = 200 * 100;
887 rdev->clock.default_mclk = mclk;
2817 rdev->pm.power_state[state_index].clock_info[0].mclk = RBIOS32(offset + 0x5 + 0x2);
2819 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2891 rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
H A Dradeon.h1038 u32 mclk; member in struct:radeon_pm_clock_info
1070 /* write locked while reprogramming mclk */
1086 fixed20_12 mclk; member in struct:radeon_pm
H A Dr100.c300 clock_info[rdev->pm.requested_clock_mode_index].mclk,
3355 mclk_ff = rdev->pm.mclk;
H A Dr600.c292 clock_info[rdev->pm.requested_clock_mode_index].mclk,
/freebsd-11-stable/sys/dev/sound/macio/
H A Di2s.c451 u_int mclk, mdiv, sdiv; local
467 mclk = rate * MCLK_FS;
471 if ((clksrc[i].cs_clock % mclk) == 0) {
473 mdiv = clksrc[i].cs_clock / mclk;
/freebsd-11-stable/sys/dev/cxgb/common/
H A Dcxgb_t3_hw.c628 VPD_ENTRY(mclk, 6); /* mem clock */
883 p->mclk = simple_strtoul(vpd.mclk_data, NULL, 10);
4159 if (vpd->mclk) {
4162 if (mc7_init(&adapter->pmrx, vpd->mclk, vpd->mem_timing) ||
4163 mc7_init(&adapter->pmtx, vpd->mclk, vpd->mem_timing) ||
4164 mc7_init(&adapter->cm, vpd->mclk, vpd->mem_timing) ||
4498 if (adapter->params.vpd.mclk) {
H A Dcxgb_common.h351 unsigned int mclk; member in struct:vpd_params

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