Lines Matching refs:mclk
164 u32 sclk, mclk;
179 * mclk and vddci.
186 mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
187 clock_info[rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx].mclk;
189 mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
190 clock_info[rdev->pm.requested_clock_mode_index].mclk;
192 if (mclk > rdev->pm.default_mclk)
193 mclk = rdev->pm.default_mclk;
222 if (rdev->asic->pm.set_memory_clock && (mclk != rdev->pm.current_mclk)) {
224 radeon_set_memory_clock(rdev, mclk);
226 rdev->pm.current_mclk = mclk;
227 DRM_DEBUG_DRIVER("Setting: m: %d\n", mclk);
333 clock_info->mclk * 10,