Searched refs:max_limits (Results 1 - 12 of 12) sorted by relevance

/linux-master/drivers/gpu/drm/radeon/
H A Dbtc_dpm.h48 const struct radeon_clock_and_voltage_limits *max_limits,
H A Dbtc_dpm.c1240 const struct radeon_clock_and_voltage_limits *max_limits,
1253 max_limits->sclk,
1260 max_limits->mclk,
2069 struct radeon_clock_and_voltage_limits *max_limits; local
2081 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
2083 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
2086 if (ps->high.mclk > max_limits->mclk)
2087 ps->high.mclk = max_limits->mclk;
2088 if (ps->high.sclk > max_limits->sclk)
2089 ps->high.sclk = max_limits
1239 btc_adjust_clock_combinations(struct radeon_device *rdev, const struct radeon_clock_and_voltage_limits *max_limits, struct rv7xx_pl *pl) argument
[all...]
H A Dni_dpm.c789 struct radeon_clock_and_voltage_limits *max_limits; local
802 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
804 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
808 if (ps->performance_levels[i].mclk > max_limits->mclk)
809 ps->performance_levels[i].mclk = max_limits->mclk;
810 if (ps->performance_levels[i].sclk > max_limits->sclk)
811 ps->performance_levels[i].sclk = max_limits->sclk;
812 if (ps->performance_levels[i].vddc > max_limits->vddc)
813 ps->performance_levels[i].vddc = max_limits->vddc;
814 if (ps->performance_levels[i].vddci > max_limits
[all...]
H A Dci_dpm.c770 struct radeon_clock_and_voltage_limits *max_limits; local
795 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
797 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
801 if (ps->performance_levels[i].mclk > max_limits->mclk)
802 ps->performance_levels[i].mclk = max_limits->mclk;
803 if (ps->performance_levels[i].sclk > max_limits->sclk)
804 ps->performance_levels[i].sclk = max_limits->sclk;
3890 const struct radeon_clock_and_voltage_limits *max_limits; local
3894 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
3896 max_limits
3939 const struct radeon_clock_and_voltage_limits *max_limits; local
[all...]
H A Dsi_dpm.c2906 struct radeon_clock_and_voltage_limits *max_limits; local
2963 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
2965 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
2973 if (ps->performance_levels[i].mclk > max_limits->mclk)
2974 ps->performance_levels[i].mclk = max_limits->mclk;
2975 if (ps->performance_levels[i].sclk > max_limits->sclk)
2976 ps->performance_levels[i].sclk = max_limits->sclk;
2977 if (ps->performance_levels[i].vddc > max_limits->vddc)
2978 ps->performance_levels[i].vddc = max_limits->vddc;
2979 if (ps->performance_levels[i].vddci > max_limits
[all...]
H A Dkv_dpm.c1947 struct radeon_clock_and_voltage_limits *max_limits = local
1958 mclk = max_limits->mclk;
1962 stable_p_state_sclk = (max_limits->sclk * 75) / 100;
2081 struct radeon_clock_and_voltage_limits *max_limits = local
2083 u32 mclk = max_limits->mclk;
/linux-master/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
H A Dvega10_hwmgr.c3271 const struct phm_clock_and_voltage_limits *max_limits; local
3287 max_limits = adev->pm.ac_power ?
3295 max_limits->mclk)
3297 max_limits->mclk;
3299 max_limits->sclk)
3301 max_limits->sclk;
3318 max_limits = &(hwmgr->dyn_state.max_clock_voltage_on_ac);
3319 stable_pstate_sclk = (max_limits->sclk *
3335 stable_pstate_mclk = max_limits->mclk;
3360 sclk = (minimum_clocks.engineClock > max_limits
4358 struct phm_clock_and_voltage_limits *max_limits = local
[all...]
H A Dsmu7_hwmgr.c3327 const struct phm_clock_and_voltage_limits *max_limits; local
3341 max_limits = adev->pm.ac_power ?
3348 if (smu7_ps->performance_levels[i].memory_clock > max_limits->mclk)
3349 smu7_ps->performance_levels[i].memory_clock = max_limits->mclk;
3350 if (smu7_ps->performance_levels[i].engine_clock > max_limits->sclk)
3351 smu7_ps->performance_levels[i].engine_clock = max_limits->sclk;
3360 max_limits = &(hwmgr->dyn_state.max_clock_voltage_on_ac);
3361 stable_pstate_sclk = (max_limits->sclk * 75) / 100;
3376 stable_pstate_mclk = max_limits->mclk;
3411 sclk = (minimum_clocks.engineClock > max_limits
[all...]
H A Dvega12_hwmgr.c1821 struct phm_clock_and_voltage_limits *max_limits =
1824 info->engine_max_clock = max_limits->sclk;
1825 info->memory_max_clock = max_limits->mclk;
H A Dvega20_hwmgr.c2794 struct phm_clock_and_voltage_limits *max_limits =
2797 info->engine_max_clock = max_limits->sclk;
2798 info->memory_max_clock = max_limits->mclk;
/linux-master/drivers/gpu/drm/amd/pm/legacy-dpm/
H A Dsi_dpm.c3283 const struct amdgpu_clock_and_voltage_limits *max_limits,
3296 max_limits->sclk,
3303 max_limits->mclk,
3426 struct amdgpu_clock_and_voltage_limits *max_limits; local
3480 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
3482 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
3490 if (ps->performance_levels[i].mclk > max_limits->mclk)
3491 ps->performance_levels[i].mclk = max_limits->mclk;
3492 if (ps->performance_levels[i].sclk > max_limits->sclk)
3493 ps->performance_levels[i].sclk = max_limits
3282 btc_adjust_clock_combinations(struct amdgpu_device *adev, const struct amdgpu_clock_and_voltage_limits *max_limits, struct rv7xx_pl *pl) argument
[all...]
H A Dkv_dpm.c2207 struct amdgpu_clock_and_voltage_limits *max_limits = local
2218 mclk = max_limits->mclk;
2222 stable_p_state_sclk = (max_limits->sclk * 75) / 100;
2341 struct amdgpu_clock_and_voltage_limits *max_limits = local
2343 u32 mclk = max_limits->mclk;

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