Searched refs:mask2 (Results 1 - 25 of 66) sorted by relevance

123

/linux-master/tools/testing/selftests/bpf/progs/
H A Dcpumask_success.c27 struct bpf_cpumask *mask1, *mask2, *mask3, *mask4; local
33 mask2 = create_cpumask();
34 if (!mask2) {
43 bpf_cpumask_release(mask2);
51 bpf_cpumask_release(mask2);
58 *out2 = mask2;
181 struct bpf_cpumask *mask1, *mask2; local
191 mask2 = create_cpumask();
192 if (!mask2)
196 bpf_cpumask_set_cpu(1, mask2);
245 struct bpf_cpumask *mask1, *mask2, *dst1, *dst2; local
292 struct bpf_cpumask *mask1, *mask2, *dst1, *dst2; local
334 struct bpf_cpumask *mask1, *mask2, *dst1, *dst2; local
510 struct bpf_cpumask *mask1, *mask2; local
[all...]
/linux-master/drivers/ras/amd/atl/
H A Dsystem.c67 static void df3p5_get_masks_shifts(u32 mask0, u32 mask1, u32 mask2) argument
75 df_cfg.socket_id_mask = FIELD_GET(DF4_SOCKET_ID_MASK, mask2);
76 df_cfg.die_id_mask = FIELD_GET(DF4_DIE_ID_MASK, mask2);
79 static void df4_get_masks_shifts(u32 mask0, u32 mask1, u32 mask2) argument
81 df3p5_get_masks_shifts(mask0, mask1, mask2);
96 u32 mask0, mask1, mask2; local
107 if (df_indirect_read_broadcast(0, 4, 0x1B8, &mask2))
110 df4_get_masks_shifts(mask0, mask1, mask2);
/linux-master/drivers/soc/fsl/qe/
H A Dgpio.c242 u32 mask2 = 0x3 << (QE_PIO_PINS - (pin % (QE_PIO_PINS / 2) + 1) * 2); local
249 qe_clrsetbits_be32(&regs->cpdir2, mask2,
250 sregs->cpdir2 & mask2);
251 qe_clrsetbits_be32(&regs->cppar2, mask2,
252 sregs->cppar2 & mask2);
254 qe_clrsetbits_be32(&regs->cpdir1, mask2,
255 sregs->cpdir1 & mask2);
256 qe_clrsetbits_be32(&regs->cppar1, mask2,
257 sregs->cppar1 & mask2);
/linux-master/arch/mips/sgi-ip22/
H A Dip22-int.c114 u8 mask2; local
118 mask2 = sgint->vmeistat & sgint->cmeimask0;
119 irq = lc2msk_to_irqnr[mask2];
136 u8 mask2; local
140 mask2 = sgint->vmeistat & sgint->cmeimask1;
141 irq = lc3msk_to_irqnr[mask2];
/linux-master/fs/orangefs/
H A Dorangefs-debugfs.c64 __u64 mask2; member in struct:client_debug_mask
457 c_mask.mask2);
544 (unsigned long long *)&(cdm_array[i].mask2));
756 (mask->mask2 & cdm_array[index].mask2)) {
800 (c_mask->mask2 == cdm_array[client_all_index].mask2)) {
807 (c_mask->mask2 == cdm_array[client_verbose_index].mask2)) {
876 (**sane_mask).mask2
[all...]
/linux-master/sound/pci/ice1712/
H A Dwm8776.c136 .mask2 = WM8776_DACVOL_MASK,
146 .mask2 = WM8776_DAC_PL_RR,
162 .mask2 = WM8776_HPVOL_MASK,
180 .mask2 = WM8776_VOL_HPZCEN,
207 .mask2 = WM8776_PHASE_INVERTR,
223 .mask2 = WM8776_ADC_GAIN_MASK,
233 .mask2 = WM8776_ADC_MUTER,
488 val2 = wm->regs[wm->ctl[n].reg2] & wm->ctl[n].mask2;
489 val2 >>= __ffs(wm->ctl[n].mask2);
528 val &= ~wm->ctl[n].mask2;
[all...]
H A Dwm8766.c37 .mask2 = WM8766_VOL_MASK,
48 .mask2 = WM8766_VOL_MASK,
59 .mask2 = WM8766_VOL_MASK,
218 val2 = wm->regs[wm->ctl[n].reg2] & wm->ctl[n].mask2;
219 val2 >>= __ffs(wm->ctl[n].mask2);
258 val &= ~wm->ctl[n].mask2;
259 val |= regval2 << __ffs(wm->ctl[n].mask2);
265 val = wm->regs[wm->ctl[n].reg2] & ~wm->ctl[n].mask2;
266 val |= regval2 << __ffs(wm->ctl[n].mask2);
/linux-master/drivers/net/wireless/ath/ath9k/
H A Dar9002_mac.c36 u32 mask2 = 0; local
67 mask2 |= ATH9K_INT_TIM;
69 mask2 |= ATH9K_INT_DTIM;
71 mask2 |= ATH9K_INT_DTIMSYNC;
73 mask2 |= ATH9K_INT_CABEND;
75 mask2 |= ATH9K_INT_GTT;
77 mask2 |= ATH9K_INT_CST;
79 mask2 |= ATH9K_INT_TSFOOR;
134 *masked |= mask2;
/linux-master/lib/
H A Dcpumask_kunit.c26 #define EXPECT_FOR_EACH_CPU_OP_EQ(test, op, mask1, mask2) \
29 const cpumask_t *m2 = (mask2); \
34 for_each_cpu_##op(cpu, mask1, mask2) \
/linux-master/drivers/gpu/drm/amd/display/dc/irq/dcn32/
H A Dirq_service_dcn32.c209 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
219 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
221 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
223 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\
233 reg2 ## __ ## mask2 ## _MASK,\
235 reg2 ## __ ## mask2 ## _MASK \
/linux-master/drivers/gpu/drm/amd/display/dc/irq/dcn35/
H A Dirq_service_dcn35.c207 #define IRQ_REG_ENTRY(base, block, reg_num, reg1, mask1, reg2, mask2)\
217 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
219 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
221 #define IRQ_REG_ENTRY_DMUB(base, reg1, mask1, reg2, mask2)\
231 reg2 ## __ ## mask2 ## _MASK,\
233 reg2 ## __ ## mask2 ## _MASK \
/linux-master/drivers/gpu/drm/amd/display/dc/irq/dcn315/
H A Dirq_service_dcn315.c215 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
225 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
227 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
229 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\
239 reg2 ## __ ## mask2 ## _MASK,\
241 reg2 ## __ ## mask2 ## _MASK \
/linux-master/drivers/gpu/drm/amd/display/dc/irq/dcn302/
H A Dirq_service_dcn302.c195 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
203 .ack_mask = block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
204 .ack_value = block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
213 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\
223 reg2 ## __ ## mask2 ## _MASK,\
225 reg2 ## __ ## mask2 ## _MASK \
/linux-master/drivers/gpu/drm/amd/display/dc/irq/dcn30/
H A Dirq_service_dcn30.c220 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
230 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
232 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
234 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\
244 reg2 ## __ ## mask2 ## _MASK,\
246 reg2 ## __ ## mask2 ## _MASK \
/linux-master/drivers/gpu/drm/amd/display/dc/irq/dcn31/
H A Dirq_service_dcn31.c208 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
218 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
220 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
222 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\
232 reg2 ## __ ## mask2 ## _MASK,\
234 reg2 ## __ ## mask2 ## _MASK \
/linux-master/drivers/gpu/drm/amd/display/dc/irq/dcn314/
H A Dirq_service_dcn314.c210 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
220 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
222 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
224 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\
234 reg2 ## __ ## mask2 ## _MASK,\
236 reg2 ## __ ## mask2 ## _MASK \
/linux-master/drivers/gpu/drm/amd/display/dc/irq/dcn21/
H A Dirq_service_dcn21.c213 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
223 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
225 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
227 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\
237 reg2 ## __ ## mask2 ## _MASK,\
239 reg2 ## __ ## mask2 ## _MASK \
/linux-master/drivers/gpu/drm/amd/display/dc/irq/dcn351/
H A Dirq_service_dcn351.c186 #define IRQ_REG_ENTRY(base, block, reg_num, reg1, mask1, reg2, mask2)\
196 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
198 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
200 #define IRQ_REG_ENTRY_DMUB(base, reg1, mask1, reg2, mask2)\
210 reg2 ## __ ## mask2 ## _MASK,\
212 reg2 ## __ ## mask2 ## _MASK \
/linux-master/arch/alpha/kernel/
H A Dsys_titan.c70 unsigned long mask0, mask1, mask2, mask3, dummy;
76 mask2 = mask & titan_cpu_irq_affinity[2];
81 else if (bcpu == 2) mask2 |= isa_enable;
95 *dim2 = mask2;
69 unsigned long mask0, mask1, mask2, mask3, dummy; local
/linux-master/drivers/net/hamradio/
H A Dbaycom_par.c206 unsigned int data, mask, mask2, descx; local
235 for(mask = 0x1fe00, mask2 = 0xfc00, i = 0;
236 i < PAR96_BURSTBITS; i++, mask <<= 1, mask2 <<= 1)
237 if ((bc->modem.par96.dcd_shreg & mask) == mask2)
240 for(mask = 0x1fe00, mask2 = 0x1fe00, i = 0;
241 i < PAR96_BURSTBITS; i++, mask <<= 1, mask2 <<= 1)
242 if (((bc->modem.par96.dcd_shreg & mask) == mask2) &&
/linux-master/fs/affs/
H A Dbitmap.c122 u32 blk, bmap, bit, mask, mask2, tmp; local
208 mask2 = mask = 1 << (bit & 31);
212 while ((mask2 <<= 1)) {
213 if (!(tmp & mask2))
216 mask |= mask2;
/linux-master/drivers/media/test-drivers/vidtv/
H A Dvidtv_pes.c90 u64 mask2; local
97 mask2 = GENMASK_ULL(29, 15);
103 pts_dts.pts2 = cpu_to_be16(((args->pts & mask2) >> 14) | 0x1);
107 pts_dts.dts2 = cpu_to_be16(((args->dts & mask2) >> 14) | 0x1);
115 pts.pts2 = cpu_to_be16(((args->pts & mask2) >> 14) | 0x1);
/linux-master/drivers/gpu/drm/amd/display/dc/
H A Ddc_helper.c293 uint8_t shift2, uint32_t mask2, uint32_t *field_value2)
297 *field_value2 = get_reg_field_value_ex(reg_val, mask2, shift2);
303 uint8_t shift2, uint32_t mask2, uint32_t *field_value2,
308 *field_value2 = get_reg_field_value_ex(reg_val, mask2, shift2);
315 uint8_t shift2, uint32_t mask2, uint32_t *field_value2,
321 *field_value2 = get_reg_field_value_ex(reg_val, mask2, shift2);
329 uint8_t shift2, uint32_t mask2, uint32_t *field_value2,
336 *field_value2 = get_reg_field_value_ex(reg_val, mask2, shift2);
345 uint8_t shift2, uint32_t mask2, uint32_t *field_value2,
353 *field_value2 = get_reg_field_value_ex(reg_val, mask2, shift
291 generic_reg_get2(const struct dc_context *ctx, uint32_t addr, uint8_t shift1, uint32_t mask1, uint32_t *field_value1, uint8_t shift2, uint32_t mask2, uint32_t *field_value2) argument
301 generic_reg_get3(const struct dc_context *ctx, uint32_t addr, uint8_t shift1, uint32_t mask1, uint32_t *field_value1, uint8_t shift2, uint32_t mask2, uint32_t *field_value2, uint8_t shift3, uint32_t mask3, uint32_t *field_value3) argument
313 generic_reg_get4(const struct dc_context *ctx, uint32_t addr, uint8_t shift1, uint32_t mask1, uint32_t *field_value1, uint8_t shift2, uint32_t mask2, uint32_t *field_value2, uint8_t shift3, uint32_t mask3, uint32_t *field_value3, uint8_t shift4, uint32_t mask4, uint32_t *field_value4) argument
327 generic_reg_get5(const struct dc_context *ctx, uint32_t addr, uint8_t shift1, uint32_t mask1, uint32_t *field_value1, uint8_t shift2, uint32_t mask2, uint32_t *field_value2, uint8_t shift3, uint32_t mask3, uint32_t *field_value3, uint8_t shift4, uint32_t mask4, uint32_t *field_value4, uint8_t shift5, uint32_t mask5, uint32_t *field_value5) argument
343 generic_reg_get6(const struct dc_context *ctx, uint32_t addr, uint8_t shift1, uint32_t mask1, uint32_t *field_value1, uint8_t shift2, uint32_t mask2, uint32_t *field_value2, uint8_t shift3, uint32_t mask3, uint32_t *field_value3, uint8_t shift4, uint32_t mask4, uint32_t *field_value4, uint8_t shift5, uint32_t mask5, uint32_t *field_value5, uint8_t shift6, uint32_t mask6, uint32_t *field_value6) argument
361 generic_reg_get7(const struct dc_context *ctx, uint32_t addr, uint8_t shift1, uint32_t mask1, uint32_t *field_value1, uint8_t shift2, uint32_t mask2, uint32_t *field_value2, uint8_t shift3, uint32_t mask3, uint32_t *field_value3, uint8_t shift4, uint32_t mask4, uint32_t *field_value4, uint8_t shift5, uint32_t mask5, uint32_t *field_value5, uint8_t shift6, uint32_t mask6, uint32_t *field_value6, uint8_t shift7, uint32_t mask7, uint32_t *field_value7) argument
381 generic_reg_get8(const struct dc_context *ctx, uint32_t addr, uint8_t shift1, uint32_t mask1, uint32_t *field_value1, uint8_t shift2, uint32_t mask2, uint32_t *field_value2, uint8_t shift3, uint32_t mask3, uint32_t *field_value3, uint8_t shift4, uint32_t mask4, uint32_t *field_value4, uint8_t shift5, uint32_t mask5, uint32_t *field_value5, uint8_t shift6, uint32_t mask6, uint32_t *field_value6, uint8_t shift7, uint32_t mask7, uint32_t *field_value7, uint8_t shift8, uint32_t mask8, uint32_t *field_value8) argument
[all...]
/linux-master/include/linux/
H A Dcpumask.h323 * @mask2: the second cpumask pointer
327 * cpumask_and(&tmp, &mask1, &mask2);
333 #define for_each_cpu_and(cpu, mask1, mask2) \
334 for_each_and_bit(cpu, cpumask_bits(mask1), cpumask_bits(mask2), small_cpumask_bits)
341 * @mask2: the second cpumask pointer
345 * cpumask_andnot(&tmp, &mask1, &mask2);
351 #define for_each_cpu_andnot(cpu, mask1, mask2) \
352 for_each_andnot_bit(cpu, cpumask_bits(mask1), cpumask_bits(mask2), small_cpumask_bits)
358 * @mask2: the second cpumask pointer
362 * cpumask_or(&tmp, &mask1, &mask2);
[all...]
/linux-master/include/uapi/linux/
H A Dserial.h90 unsigned char mask2, match2; member in struct:serial_multiport_struct

Completed in 583 milliseconds

123