1/* SPDX-License-Identifier: GPL-1.0+ WITH Linux-syscall-note */ 2/* 3 * include/linux/serial.h 4 * 5 * Copyright (C) 1992 by Theodore Ts'o. 6 * 7 * Redistribution of this file is permitted under the terms of the GNU 8 * Public License (GPL) 9 */ 10 11#ifndef _UAPI_LINUX_SERIAL_H 12#define _UAPI_LINUX_SERIAL_H 13 14#include <linux/const.h> 15#include <linux/types.h> 16 17#include <linux/tty_flags.h> 18 19 20struct serial_struct { 21 int type; 22 int line; 23 unsigned int port; 24 int irq; 25 int flags; 26 int xmit_fifo_size; 27 int custom_divisor; 28 int baud_base; 29 unsigned short close_delay; 30 char io_type; 31 char reserved_char[1]; 32 int hub6; 33 unsigned short closing_wait; /* time to wait before closing */ 34 unsigned short closing_wait2; /* no longer used... */ 35 unsigned char *iomem_base; 36 unsigned short iomem_reg_shift; 37 unsigned int port_high; 38 unsigned long iomap_base; /* cookie passed into ioremap */ 39}; 40 41/* 42 * For the close wait times, 0 means wait forever for serial port to 43 * flush its output. 65535 means don't wait at all. 44 */ 45#define ASYNC_CLOSING_WAIT_INF 0 46#define ASYNC_CLOSING_WAIT_NONE 65535 47 48/* 49 * These are the supported serial types. 50 */ 51#define PORT_UNKNOWN 0 52#define PORT_8250 1 53#define PORT_16450 2 54#define PORT_16550 3 55#define PORT_16550A 4 56#define PORT_CIRRUS 5 57#define PORT_16650 6 58#define PORT_16650V2 7 59#define PORT_16750 8 60#define PORT_STARTECH 9 61#define PORT_16C950 10 /* Oxford Semiconductor */ 62#define PORT_16654 11 63#define PORT_16850 12 64#define PORT_RSA 13 /* RSA-DV II/S card */ 65#define PORT_MAX 13 66 67#define SERIAL_IO_PORT 0 68#define SERIAL_IO_HUB6 1 69#define SERIAL_IO_MEM 2 70#define SERIAL_IO_MEM32 3 71#define SERIAL_IO_AU 4 72#define SERIAL_IO_TSI 5 73#define SERIAL_IO_MEM32BE 6 74#define SERIAL_IO_MEM16 7 75 76#define UART_CLEAR_FIFO 0x01 77#define UART_USE_FIFO 0x02 78#define UART_STARTECH 0x04 79#define UART_NATSEMI 0x08 80 81 82/* 83 * Multiport serial configuration structure --- external structure 84 */ 85struct serial_multiport_struct { 86 int irq; 87 int port1; 88 unsigned char mask1, match1; 89 int port2; 90 unsigned char mask2, match2; 91 int port3; 92 unsigned char mask3, match3; 93 int port4; 94 unsigned char mask4, match4; 95 int port_monitor; 96 int reserved[32]; 97}; 98 99/* 100 * Serial input interrupt line counters -- external structure 101 * Four lines can interrupt: CTS, DSR, RI, DCD 102 */ 103struct serial_icounter_struct { 104 int cts, dsr, rng, dcd; 105 int rx, tx; 106 int frame, overrun, parity, brk; 107 int buf_overrun; 108 int reserved[9]; 109}; 110 111/** 112 * struct serial_rs485 - serial interface for controlling RS485 settings. 113 * @flags: RS485 feature flags. 114 * @delay_rts_before_send: Delay before send (milliseconds). 115 * @delay_rts_after_send: Delay after send (milliseconds). 116 * @addr_recv: Receive filter for RS485 addressing mode 117 * (used only when %SER_RS485_ADDR_RECV is set). 118 * @addr_dest: Destination address for RS485 addressing mode 119 * (used only when %SER_RS485_ADDR_DEST is set). 120 * @padding0: Padding (set to zero). 121 * @padding1: Padding (set to zero). 122 * @padding: Deprecated, use @padding0 and @padding1 instead. 123 * Do not use with @addr_recv and @addr_dest (due to 124 * overlap). 125 * 126 * Serial interface for controlling RS485 settings on chips with suitable 127 * support. Set with TIOCSRS485 and get with TIOCGRS485 if supported by your 128 * platform. The set function returns the new state, with any unsupported bits 129 * reverted appropriately. 130 * 131 * The flag bits are: 132 * 133 * * %SER_RS485_ENABLED - RS485 enabled. 134 * * %SER_RS485_RTS_ON_SEND - Logical level for RTS pin when sending. 135 * * %SER_RS485_RTS_AFTER_SEND - Logical level for RTS pin after sent. 136 * * %SER_RS485_RX_DURING_TX - Full-duplex RS485 line. 137 * * %SER_RS485_TERMINATE_BUS - Enable bus termination (if supported). 138 * * %SER_RS485_ADDRB - Enable RS485 addressing mode. 139 * * %SER_RS485_ADDR_RECV - Receive address filter (enables @addr_recv). Requires %SER_RS485_ADDRB. 140 * * %SER_RS485_ADDR_DEST - Destination address (enables @addr_dest). Requires %SER_RS485_ADDRB. 141 * * %SER_RS485_MODE_RS422 - Enable RS422. Requires %SER_RS485_ENABLED. 142 */ 143struct serial_rs485 { 144 __u32 flags; 145#define SER_RS485_ENABLED _BITUL(0) 146#define SER_RS485_RTS_ON_SEND _BITUL(1) 147#define SER_RS485_RTS_AFTER_SEND _BITUL(2) 148/* Placeholder for bit 3: SER_RS485_RTS_BEFORE_SEND, which isn't used anymore */ 149#define SER_RS485_RX_DURING_TX _BITUL(4) 150#define SER_RS485_TERMINATE_BUS _BITUL(5) 151#define SER_RS485_ADDRB _BITUL(6) 152#define SER_RS485_ADDR_RECV _BITUL(7) 153#define SER_RS485_ADDR_DEST _BITUL(8) 154#define SER_RS485_MODE_RS422 _BITUL(9) 155 156 __u32 delay_rts_before_send; 157 __u32 delay_rts_after_send; 158 159 /* The fields below are defined by flags */ 160 union { 161 __u32 padding[5]; /* Memory is cheap, new structs are a pain */ 162 163 struct { 164 __u8 addr_recv; 165 __u8 addr_dest; 166 __u8 padding0[2]; 167 __u32 padding1[4]; 168 }; 169 }; 170}; 171 172/* 173 * Serial interface for controlling ISO7816 settings on chips with suitable 174 * support. Set with TIOCSISO7816 and get with TIOCGISO7816 if supported by 175 * your platform. 176 */ 177struct serial_iso7816 { 178 __u32 flags; /* ISO7816 feature flags */ 179#define SER_ISO7816_ENABLED (1 << 0) 180#define SER_ISO7816_T_PARAM (0x0f << 4) 181#define SER_ISO7816_T(t) (((t) & 0x0f) << 4) 182 __u32 tg; 183 __u32 sc_fi; 184 __u32 sc_di; 185 __u32 clk; 186 __u32 reserved[5]; 187}; 188 189#endif /* _UAPI_LINUX_SERIAL_H */ 190