Searched refs:layers (Results 1 - 25 of 80) sorted by relevance

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/linux-master/security/landlock/
H A Druleset.c100 const struct landlock_layer (*const layers)[], const u32 num_layers,
115 new_rule = kzalloc(struct_size(new_rule, layers, new_num_layers),
129 memcpy(new_rule->layers, layers,
130 flex_array_size(new_rule, layers, num_layers));
133 new_rule->layers[new_rule->num_layers - 1] = *new_layer;
187 * @layers: One or multiple layers to be copied into the new rule.
188 * @num_layers: The number of @layers entries.
190 * When user space requests to add a new rule to a ruleset, @layers onl
99 create_rule(const struct landlock_id id, const struct landlock_layer (*const layers)[], const u32 num_layers, const struct landlock_layer *const new_layer) argument
199 insert_rule(struct landlock_ruleset *const ruleset, const struct landlock_id id, const struct landlock_layer (*const layers)[], const size_t num_layers) argument
298 struct landlock_layer layers[] = { { local
343 struct landlock_layer layers[] = { { local
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/linux-master/drivers/edac/
H A Dpasemi_edac.c183 struct edac_mc_layer layers[2]; local
200 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
201 layers[0].size = PASEMI_EDAC_NR_CSROWS;
202 layers[0].is_virt_csrow = true;
203 layers[1].type = EDAC_MC_LAYER_CHANNEL;
204 layers[1].size = PASEMI_EDAC_NR_CHANS;
205 layers[1].is_virt_csrow = false;
206 mci = edac_mc_alloc(system_mmc_id++, ARRAY_SIZE(layers), layers,
H A Damd76x_edac.c237 struct edac_mc_layer layers[2]; local
246 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
247 layers[0].size = AMD76X_NR_CSROWS;
248 layers[0].is_virt_csrow = true;
249 layers[1].type = EDAC_MC_LAYER_CHANNEL;
250 layers[1].size = 1;
251 layers[1].is_virt_csrow = false;
252 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, 0);
H A Dr82600_edac.c271 struct edac_mc_layer layers[2]; local
285 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
286 layers[0].size = R82600_NR_CSROWS;
287 layers[0].is_virt_csrow = true;
288 layers[1].type = EDAC_MC_LAYER_CHANNEL;
289 layers[1].size = R82600_NR_CHANS;
290 layers[1].is_virt_csrow = false;
291 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, 0);
H A Di82860_edac.c187 struct edac_mc_layer layers[2]; local
200 layers[0].type = EDAC_MC_LAYER_CHANNEL;
201 layers[0].size = 2;
202 layers[0].is_virt_csrow = true;
203 layers[1].type = EDAC_MC_LAYER_SLOT;
204 layers[1].size = 8;
205 layers[1].is_virt_csrow = true;
206 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, 0);
H A Dhighbank_mc_edac.c149 struct edac_mc_layer layers[2]; local
163 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
164 layers[0].size = 1;
165 layers[0].is_virt_csrow = true;
166 layers[1].type = EDAC_MC_LAYER_CHANNEL;
167 layers[1].size = 1;
168 layers[1].is_virt_csrow = false;
169 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers,
H A Di82443bxgx_edac.c234 struct edac_mc_layer layers[2]; local
248 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
249 layers[0].size = I82443BXGX_NR_CSROWS;
250 layers[0].is_virt_csrow = true;
251 layers[1].type = EDAC_MC_LAYER_CHANNEL;
252 layers[1].size = I82443BXGX_NR_CHANS;
253 layers[1].is_virt_csrow = false;
254 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, 0);
H A Di3000_edac.c313 struct edac_mc_layer layers[2]; local
356 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
357 layers[0].size = I3000_RANKS / nr_channels;
358 layers[0].is_virt_csrow = true;
359 layers[1].type = EDAC_MC_LAYER_CHANNEL;
360 layers[1].size = nr_channels;
361 layers[1].is_virt_csrow = false;
362 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, 0);
H A Dx38_edac.c322 struct edac_mc_layer layers[2]; local
338 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
339 layers[0].size = X38_RANKS;
340 layers[0].is_virt_csrow = true;
341 layers[1].type = EDAC_MC_LAYER_CHANNEL;
342 layers[1].size = x38_channel_num;
343 layers[1].is_virt_csrow = false;
344 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, 0);
H A Daspeed_edac.c282 struct edac_mc_layer layers[2]; local
307 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
308 layers[0].size = 1;
309 layers[0].is_virt_csrow = true;
310 layers[1].type = EDAC_MC_LAYER_CHANNEL;
311 layers[1].size = 1;
312 layers[1].is_virt_csrow = false;
314 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, 0);
H A Dcell_edac.c172 struct edac_mc_layer layers[2]; local
202 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
203 layers[0].size = 1;
204 layers[0].is_virt_csrow = true;
205 layers[1].type = EDAC_MC_LAYER_CHANNEL;
206 layers[1].size = num_chans;
207 layers[1].is_virt_csrow = false;
208 mci = edac_mc_alloc(pdev->id, ARRAY_SIZE(layers), layers,
H A Docteon_edac-lmc.c228 struct edac_mc_layer layers[1]; local
233 layers[0].type = EDAC_MC_LAYER_CHANNEL;
234 layers[0].size = 1;
235 layers[0].is_virt_csrow = false;
246 mci = edac_mc_alloc(mc, ARRAY_SIZE(layers), layers, sizeof(struct octeon_lmc_pvt));
278 mci = edac_mc_alloc(mc, ARRAY_SIZE(layers), layers, sizeof(struct octeon_lmc_pvt));
H A Dbluefield_edac.c246 struct edac_mc_layer layers[1]; local
273 layers[0].type = EDAC_MC_LAYER_SLOT;
274 layers[0].size = dimm_count;
275 layers[0].is_virt_csrow = true;
277 mci = edac_mc_alloc(mc_idx, ARRAY_SIZE(layers), layers, sizeof(*priv));
H A Di82875p_edac.c391 struct edac_mc_layer layers[2]; local
406 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
407 layers[0].size = I82875P_NR_CSROWS(nr_chans);
408 layers[0].is_virt_csrow = true;
409 layers[1].type = EDAC_MC_LAYER_CHANNEL;
410 layers[1].size = nr_chans;
411 layers[1].is_virt_csrow = false;
412 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, sizeof(*pvt));
H A Di82975x_edac.c467 struct edac_mc_layer layers[2]; local
540 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
541 layers[0].size = I82975X_NR_DIMMS;
542 layers[0].is_virt_csrow = true;
543 layers[1].type = EDAC_MC_LAYER_CHANNEL;
544 layers[1].size = I82975X_NR_CSROWS(chans);
545 layers[1].is_virt_csrow = false;
546 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, sizeof(*pvt));
H A Di3200_edac.c340 struct edac_mc_layer layers[2]; local
355 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
356 layers[0].size = I3200_DIMMS;
357 layers[0].is_virt_csrow = true;
358 layers[1].type = EDAC_MC_LAYER_CHANNEL;
359 layers[1].size = nr_channels;
360 layers[1].is_virt_csrow = false;
361 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers,
H A De7xxx_edac.c424 struct edac_mc_layer layers[2]; local
443 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
444 layers[0].size = E7XXX_NR_CSROWS;
445 layers[0].is_virt_csrow = true;
446 layers[1].type = EDAC_MC_LAYER_CHANNEL;
447 layers[1].size = drc_chan + 1;
448 layers[1].is_virt_csrow = false;
449 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, sizeof(*pvt));
H A Dedac_mc.c70 edac_layer_name[mci->layers[i].type],
206 kfree(mci->layers);
296 edac_layer_name[mci->layers[layer].type],
309 if (mci->layers[0].is_virt_csrow) {
326 if (pos[layer] < mci->layers[layer].size)
337 struct edac_mc_layer *layers,
354 tot_dimms *= layers[idx].size;
356 if (layers[idx].is_virt_csrow)
357 tot_csrows *= layers[idx].size;
359 tot_channels *= layers[id
335 edac_mc_alloc(unsigned int mc_num, unsigned int n_layers, struct edac_mc_layer *layers, unsigned int sz_pvt) argument
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H A Dal_mc_edac.c219 struct edac_mc_layer layers[1]; local
233 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
234 layers[0].size = 1;
235 layers[0].is_virt_csrow = false;
236 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers,
H A Dti_edac.c237 struct edac_mc_layer layers[1]; local
251 layers[0].type = EDAC_MC_LAYER_ALL_MEM;
252 layers[0].size = 1;
259 mci = edac_mc_alloc(emif_id, 1, layers, sizeof(*edac));
H A Di5400_edac.c1180 * layers here.
1182 for (channel = 0; channel < mci->layers[0].size * mci->layers[1].size;
1184 for (slot = 0; slot < mci->layers[2].size; slot++) {
1257 struct edac_mc_layer layers[3]; local
1275 layers[0].type = EDAC_MC_LAYER_BRANCH;
1276 layers[0].size = MAX_BRANCHES;
1277 layers[0].is_virt_csrow = false;
1278 layers[1].type = EDAC_MC_LAYER_CHANNEL;
1279 layers[
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/linux-master/drivers/gpu/drm/xlnx/
H A Dzynqmp_dpsub.h75 struct zynqmp_disp_layer *layers[ZYNQMP_DPSUB_NUM_LAYERS]; member in struct:zynqmp_dpsub
/linux-master/drivers/media/dvb-frontends/
H A Dtc90522.c201 int layers; local
209 layers = 0;
236 layers = (v > 0) ? 2 : 1;
284 stats->len = layers;
287 for (i = 0; i < layers; i++)
290 for (i = 0; i < layers; i++) {
298 stats->len = layers;
300 for (i = 0; i < layers; i++)
303 for (i = 0; i < layers; i++) {
336 int layers; local
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/linux-master/fs/overlayfs/
H A Dovl_entry.h60 /* Number of unique fs among layers including upper fs */
62 /* Number of data-only lower layers */
64 struct ovl_layer *layers; member in struct:ovl_fs
95 /* Number of lower layers, not including data-only layers */
103 return ofs->layers[0].mnt;
/linux-master/drivers/gpu/drm/imagination/
H A Dpvr_hwrt.c50 hwrt->max_rts = args->layers;
391 rta_ctl->max_rts = args->layers;
393 if (args->layers > 1) {
394 err = pvr_fw_object_create(pvr_dev, args->layers * SRTC_ENTRY_SIZE,
402 err = pvr_fw_object_create(pvr_dev, args->layers * RAA_ENTRY_SIZE,
422 if (args->layers > 1)
426 if (args->layers > 1)

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