1/*
2 * Intel X38 Memory Controller kernel module
3 * Copyright (C) 2008 Cluster Computing, Inc.
4 *
5 * This file may be distributed under the terms of the
6 * GNU General Public License.
7 *
8 * This file is based on i3200_edac.c
9 *
10 */
11
12#include <linux/module.h>
13#include <linux/init.h>
14#include <linux/pci.h>
15#include <linux/pci_ids.h>
16#include <linux/edac.h>
17
18#include <linux/io-64-nonatomic-lo-hi.h>
19#include "edac_module.h"
20
21#define EDAC_MOD_STR		"x38_edac"
22
23#define PCI_DEVICE_ID_INTEL_X38_HB	0x29e0
24
25#define X38_RANKS		8
26#define X38_RANKS_PER_CHANNEL	4
27#define X38_CHANNELS		2
28
29/* Intel X38 register addresses - device 0 function 0 - DRAM Controller */
30
31#define X38_MCHBAR_LOW	0x48	/* MCH Memory Mapped Register BAR */
32#define X38_MCHBAR_HIGH	0x4c
33#define X38_MCHBAR_MASK	0xfffffc000ULL	/* bits 35:14 */
34#define X38_MMR_WINDOW_SIZE	16384
35
36#define X38_TOM	0xa0	/* Top of Memory (16b)
37				 *
38				 * 15:10 reserved
39				 *  9:0  total populated physical memory
40				 */
41#define X38_TOM_MASK	0x3ff	/* bits 9:0 */
42#define X38_TOM_SHIFT 26	/* 64MiB grain */
43
44#define X38_ERRSTS	0xc8	/* Error Status Register (16b)
45				 *
46				 * 15    reserved
47				 * 14    Isochronous TBWRR Run Behind FIFO Full
48				 *       (ITCV)
49				 * 13    Isochronous TBWRR Run Behind FIFO Put
50				 *       (ITSTV)
51				 * 12    reserved
52				 * 11    MCH Thermal Sensor Event
53				 *       for SMI/SCI/SERR (GTSE)
54				 * 10    reserved
55				 *  9    LOCK to non-DRAM Memory Flag (LCKF)
56				 *  8    reserved
57				 *  7    DRAM Throttle Flag (DTF)
58				 *  6:2  reserved
59				 *  1    Multi-bit DRAM ECC Error Flag (DMERR)
60				 *  0    Single-bit DRAM ECC Error Flag (DSERR)
61				 */
62#define X38_ERRSTS_UE		0x0002
63#define X38_ERRSTS_CE		0x0001
64#define X38_ERRSTS_BITS	(X38_ERRSTS_UE | X38_ERRSTS_CE)
65
66
67/* Intel  MMIO register space - device 0 function 0 - MMR space */
68
69#define X38_C0DRB	0x200	/* Channel 0 DRAM Rank Boundary (16b x 4)
70				 *
71				 * 15:10 reserved
72				 *  9:0  Channel 0 DRAM Rank Boundary Address
73				 */
74#define X38_C1DRB	0x600	/* Channel 1 DRAM Rank Boundary (16b x 4) */
75#define X38_DRB_MASK	0x3ff	/* bits 9:0 */
76#define X38_DRB_SHIFT 26	/* 64MiB grain */
77
78#define X38_C0ECCERRLOG 0x280	/* Channel 0 ECC Error Log (64b)
79				 *
80				 * 63:48 Error Column Address (ERRCOL)
81				 * 47:32 Error Row Address (ERRROW)
82				 * 31:29 Error Bank Address (ERRBANK)
83				 * 28:27 Error Rank Address (ERRRANK)
84				 * 26:24 reserved
85				 * 23:16 Error Syndrome (ERRSYND)
86				 * 15: 2 reserved
87				 *    1  Multiple Bit Error Status (MERRSTS)
88				 *    0  Correctable Error Status (CERRSTS)
89				 */
90#define X38_C1ECCERRLOG 0x680	/* Channel 1 ECC Error Log (64b) */
91#define X38_ECCERRLOG_CE	0x1
92#define X38_ECCERRLOG_UE	0x2
93#define X38_ECCERRLOG_RANK_BITS	0x18000000
94#define X38_ECCERRLOG_SYNDROME_BITS	0xff0000
95
96#define X38_CAPID0 0xe0	/* see P.94 of spec for details */
97
98static int x38_channel_num;
99
100static int how_many_channel(struct pci_dev *pdev)
101{
102	unsigned char capid0_8b; /* 8th byte of CAPID0 */
103
104	pci_read_config_byte(pdev, X38_CAPID0 + 8, &capid0_8b);
105	if (capid0_8b & 0x20) {	/* check DCD: Dual Channel Disable */
106		edac_dbg(0, "In single channel mode\n");
107		x38_channel_num = 1;
108	} else {
109		edac_dbg(0, "In dual channel mode\n");
110		x38_channel_num = 2;
111	}
112
113	return x38_channel_num;
114}
115
116static unsigned long eccerrlog_syndrome(u64 log)
117{
118	return (log & X38_ECCERRLOG_SYNDROME_BITS) >> 16;
119}
120
121static int eccerrlog_row(int channel, u64 log)
122{
123	return ((log & X38_ECCERRLOG_RANK_BITS) >> 27) |
124		(channel * X38_RANKS_PER_CHANNEL);
125}
126
127enum x38_chips {
128	X38 = 0,
129};
130
131struct x38_dev_info {
132	const char *ctl_name;
133};
134
135struct x38_error_info {
136	u16 errsts;
137	u16 errsts2;
138	u64 eccerrlog[X38_CHANNELS];
139};
140
141static const struct x38_dev_info x38_devs[] = {
142	[X38] = {
143		.ctl_name = "x38"},
144};
145
146static struct pci_dev *mci_pdev;
147static int x38_registered = 1;
148
149
150static void x38_clear_error_info(struct mem_ctl_info *mci)
151{
152	struct pci_dev *pdev;
153
154	pdev = to_pci_dev(mci->pdev);
155
156	/*
157	 * Clear any error bits.
158	 * (Yes, we really clear bits by writing 1 to them.)
159	 */
160	pci_write_bits16(pdev, X38_ERRSTS, X38_ERRSTS_BITS,
161			 X38_ERRSTS_BITS);
162}
163
164static void x38_get_and_clear_error_info(struct mem_ctl_info *mci,
165				 struct x38_error_info *info)
166{
167	struct pci_dev *pdev;
168	void __iomem *window = mci->pvt_info;
169
170	pdev = to_pci_dev(mci->pdev);
171
172	/*
173	 * This is a mess because there is no atomic way to read all the
174	 * registers at once and the registers can transition from CE being
175	 * overwritten by UE.
176	 */
177	pci_read_config_word(pdev, X38_ERRSTS, &info->errsts);
178	if (!(info->errsts & X38_ERRSTS_BITS))
179		return;
180
181	info->eccerrlog[0] = lo_hi_readq(window + X38_C0ECCERRLOG);
182	if (x38_channel_num == 2)
183		info->eccerrlog[1] = lo_hi_readq(window + X38_C1ECCERRLOG);
184
185	pci_read_config_word(pdev, X38_ERRSTS, &info->errsts2);
186
187	/*
188	 * If the error is the same for both reads then the first set
189	 * of reads is valid.  If there is a change then there is a CE
190	 * with no info and the second set of reads is valid and
191	 * should be UE info.
192	 */
193	if ((info->errsts ^ info->errsts2) & X38_ERRSTS_BITS) {
194		info->eccerrlog[0] = lo_hi_readq(window + X38_C0ECCERRLOG);
195		if (x38_channel_num == 2)
196			info->eccerrlog[1] =
197				lo_hi_readq(window + X38_C1ECCERRLOG);
198	}
199
200	x38_clear_error_info(mci);
201}
202
203static void x38_process_error_info(struct mem_ctl_info *mci,
204				struct x38_error_info *info)
205{
206	int channel;
207	u64 log;
208
209	if (!(info->errsts & X38_ERRSTS_BITS))
210		return;
211
212	if ((info->errsts ^ info->errsts2) & X38_ERRSTS_BITS) {
213		edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1, 0, 0, 0,
214				     -1, -1, -1,
215				     "UE overwrote CE", "");
216		info->errsts = info->errsts2;
217	}
218
219	for (channel = 0; channel < x38_channel_num; channel++) {
220		log = info->eccerrlog[channel];
221		if (log & X38_ECCERRLOG_UE) {
222			edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1,
223					     0, 0, 0,
224					     eccerrlog_row(channel, log),
225					     -1, -1,
226					     "x38 UE", "");
227		} else if (log & X38_ECCERRLOG_CE) {
228			edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1,
229					     0, 0, eccerrlog_syndrome(log),
230					     eccerrlog_row(channel, log),
231					     -1, -1,
232					     "x38 CE", "");
233		}
234	}
235}
236
237static void x38_check(struct mem_ctl_info *mci)
238{
239	struct x38_error_info info;
240
241	x38_get_and_clear_error_info(mci, &info);
242	x38_process_error_info(mci, &info);
243}
244
245static void __iomem *x38_map_mchbar(struct pci_dev *pdev)
246{
247	union {
248		u64 mchbar;
249		struct {
250			u32 mchbar_low;
251			u32 mchbar_high;
252		};
253	} u;
254	void __iomem *window;
255
256	pci_read_config_dword(pdev, X38_MCHBAR_LOW, &u.mchbar_low);
257	pci_write_config_dword(pdev, X38_MCHBAR_LOW, u.mchbar_low | 0x1);
258	pci_read_config_dword(pdev, X38_MCHBAR_HIGH, &u.mchbar_high);
259	u.mchbar &= X38_MCHBAR_MASK;
260
261	if (u.mchbar != (resource_size_t)u.mchbar) {
262		printk(KERN_ERR
263			"x38: mmio space beyond accessible range (0x%llx)\n",
264			(unsigned long long)u.mchbar);
265		return NULL;
266	}
267
268	window = ioremap(u.mchbar, X38_MMR_WINDOW_SIZE);
269	if (!window)
270		printk(KERN_ERR "x38: cannot map mmio space at 0x%llx\n",
271			(unsigned long long)u.mchbar);
272
273	return window;
274}
275
276
277static void x38_get_drbs(void __iomem *window,
278			u16 drbs[X38_CHANNELS][X38_RANKS_PER_CHANNEL])
279{
280	int i;
281
282	for (i = 0; i < X38_RANKS_PER_CHANNEL; i++) {
283		drbs[0][i] = readw(window + X38_C0DRB + 2*i) & X38_DRB_MASK;
284		drbs[1][i] = readw(window + X38_C1DRB + 2*i) & X38_DRB_MASK;
285	}
286}
287
288static bool x38_is_stacked(struct pci_dev *pdev,
289			u16 drbs[X38_CHANNELS][X38_RANKS_PER_CHANNEL])
290{
291	u16 tom;
292
293	pci_read_config_word(pdev, X38_TOM, &tom);
294	tom &= X38_TOM_MASK;
295
296	return drbs[X38_CHANNELS - 1][X38_RANKS_PER_CHANNEL - 1] == tom;
297}
298
299static unsigned long drb_to_nr_pages(
300			u16 drbs[X38_CHANNELS][X38_RANKS_PER_CHANNEL],
301			bool stacked, int channel, int rank)
302{
303	int n;
304
305	n = drbs[channel][rank];
306	if (rank > 0)
307		n -= drbs[channel][rank - 1];
308	if (stacked && (channel == 1) && drbs[channel][rank] ==
309				drbs[channel][X38_RANKS_PER_CHANNEL - 1]) {
310		n -= drbs[0][X38_RANKS_PER_CHANNEL - 1];
311	}
312
313	n <<= (X38_DRB_SHIFT - PAGE_SHIFT);
314	return n;
315}
316
317static int x38_probe1(struct pci_dev *pdev, int dev_idx)
318{
319	int rc;
320	int i, j;
321	struct mem_ctl_info *mci = NULL;
322	struct edac_mc_layer layers[2];
323	u16 drbs[X38_CHANNELS][X38_RANKS_PER_CHANNEL];
324	bool stacked;
325	void __iomem *window;
326
327	edac_dbg(0, "MC:\n");
328
329	window = x38_map_mchbar(pdev);
330	if (!window)
331		return -ENODEV;
332
333	x38_get_drbs(window, drbs);
334
335	how_many_channel(pdev);
336
337	/* FIXME: unconventional pvt_info usage */
338	layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
339	layers[0].size = X38_RANKS;
340	layers[0].is_virt_csrow = true;
341	layers[1].type = EDAC_MC_LAYER_CHANNEL;
342	layers[1].size = x38_channel_num;
343	layers[1].is_virt_csrow = false;
344	mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, 0);
345	if (!mci)
346		return -ENOMEM;
347
348	edac_dbg(3, "MC: init mci\n");
349
350	mci->pdev = &pdev->dev;
351	mci->mtype_cap = MEM_FLAG_DDR2;
352
353	mci->edac_ctl_cap = EDAC_FLAG_SECDED;
354	mci->edac_cap = EDAC_FLAG_SECDED;
355
356	mci->mod_name = EDAC_MOD_STR;
357	mci->ctl_name = x38_devs[dev_idx].ctl_name;
358	mci->dev_name = pci_name(pdev);
359	mci->edac_check = x38_check;
360	mci->ctl_page_to_phys = NULL;
361	mci->pvt_info = window;
362
363	stacked = x38_is_stacked(pdev, drbs);
364
365	/*
366	 * The dram rank boundary (DRB) reg values are boundary addresses
367	 * for each DRAM rank with a granularity of 64MB.  DRB regs are
368	 * cumulative; the last one will contain the total memory
369	 * contained in all ranks.
370	 */
371	for (i = 0; i < mci->nr_csrows; i++) {
372		unsigned long nr_pages;
373		struct csrow_info *csrow = mci->csrows[i];
374
375		nr_pages = drb_to_nr_pages(drbs, stacked,
376			i / X38_RANKS_PER_CHANNEL,
377			i % X38_RANKS_PER_CHANNEL);
378
379		if (nr_pages == 0)
380			continue;
381
382		for (j = 0; j < x38_channel_num; j++) {
383			struct dimm_info *dimm = csrow->channels[j]->dimm;
384
385			dimm->nr_pages = nr_pages / x38_channel_num;
386			dimm->grain = nr_pages << PAGE_SHIFT;
387			dimm->mtype = MEM_DDR2;
388			dimm->dtype = DEV_UNKNOWN;
389			dimm->edac_mode = EDAC_UNKNOWN;
390		}
391	}
392
393	x38_clear_error_info(mci);
394
395	rc = -ENODEV;
396	if (edac_mc_add_mc(mci)) {
397		edac_dbg(3, "MC: failed edac_mc_add_mc()\n");
398		goto fail;
399	}
400
401	/* get this far and it's successful */
402	edac_dbg(3, "MC: success\n");
403	return 0;
404
405fail:
406	iounmap(window);
407	if (mci)
408		edac_mc_free(mci);
409
410	return rc;
411}
412
413static int x38_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
414{
415	int rc;
416
417	edac_dbg(0, "MC:\n");
418
419	if (pci_enable_device(pdev) < 0)
420		return -EIO;
421
422	rc = x38_probe1(pdev, ent->driver_data);
423	if (!mci_pdev)
424		mci_pdev = pci_dev_get(pdev);
425
426	return rc;
427}
428
429static void x38_remove_one(struct pci_dev *pdev)
430{
431	struct mem_ctl_info *mci;
432
433	edac_dbg(0, "\n");
434
435	mci = edac_mc_del_mc(&pdev->dev);
436	if (!mci)
437		return;
438
439	iounmap(mci->pvt_info);
440
441	edac_mc_free(mci);
442}
443
444static const struct pci_device_id x38_pci_tbl[] = {
445	{
446	 PCI_VEND_DEV(INTEL, X38_HB), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
447	 X38},
448	{
449	 0,
450	 }			/* 0 terminated list. */
451};
452
453MODULE_DEVICE_TABLE(pci, x38_pci_tbl);
454
455static struct pci_driver x38_driver = {
456	.name = EDAC_MOD_STR,
457	.probe = x38_init_one,
458	.remove = x38_remove_one,
459	.id_table = x38_pci_tbl,
460};
461
462static int __init x38_init(void)
463{
464	int pci_rc;
465
466	edac_dbg(3, "MC:\n");
467
468	/* Ensure that the OPSTATE is set correctly for POLL or NMI */
469	opstate_init();
470
471	pci_rc = pci_register_driver(&x38_driver);
472	if (pci_rc < 0)
473		goto fail0;
474
475	if (!mci_pdev) {
476		x38_registered = 0;
477		mci_pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
478					PCI_DEVICE_ID_INTEL_X38_HB, NULL);
479		if (!mci_pdev) {
480			edac_dbg(0, "x38 pci_get_device fail\n");
481			pci_rc = -ENODEV;
482			goto fail1;
483		}
484
485		pci_rc = x38_init_one(mci_pdev, x38_pci_tbl);
486		if (pci_rc < 0) {
487			edac_dbg(0, "x38 init fail\n");
488			pci_rc = -ENODEV;
489			goto fail1;
490		}
491	}
492
493	return 0;
494
495fail1:
496	pci_unregister_driver(&x38_driver);
497
498fail0:
499	pci_dev_put(mci_pdev);
500
501	return pci_rc;
502}
503
504static void __exit x38_exit(void)
505{
506	edac_dbg(3, "MC:\n");
507
508	pci_unregister_driver(&x38_driver);
509	if (!x38_registered) {
510		x38_remove_one(mci_pdev);
511		pci_dev_put(mci_pdev);
512	}
513}
514
515module_init(x38_init);
516module_exit(x38_exit);
517
518MODULE_LICENSE("GPL");
519MODULE_AUTHOR("Cluster Computing, Inc. Hitoshi Mitake");
520MODULE_DESCRIPTION("MC support for Intel X38 memory hub controllers");
521
522module_param(edac_op_state, int, 0444);
523MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");
524