/linux-master/drivers/net/ethernet/microchip/lan966x/ |
H A D | lan966x_port.c | 31 lan_rmw(AFI_PORT_CFG_FC_SKIP_TTI_INJ_SET(1) | 54 lan_rmw(DEV_CLOCK_CFG_PCS_RX_RST_SET(1), 59 lan_rmw(DEV_MAC_ENA_CFG_RX_ENA_SET(0), 64 lan_rmw(QSYS_SW_PORT_MODE_PORT_ENA_SET(0), 69 lan_rmw(QSYS_PORT_MODE_DEQUEUE_DIS_SET(1), 74 lan_rmw(SYS_PAUSE_CFG_PAUSE_ENA_SET(0), 79 lan_rmw(QSYS_SW_PORT_MODE_TX_PFC_ENA_SET(0), 87 lan_rmw(SYS_FRONT_PORT_MODE_HDX_MODE_SET(0), 92 lan_rmw(QSYS_SW_PORT_MODE_AGING_MODE_SET(3), 97 lan_rmw(QSYS_PORT_MODE_DEQUEUE_DIS_SE [all...] |
H A D | lan966x_cbs.c | 38 lan_rmw(QSYS_SE_CFG_SE_AVB_ENA_SET(1) | 59 lan_rmw(QSYS_SE_CFG_SE_AVB_ENA_SET(1) |
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H A D | lan966x_vlan.c | 34 lan_rmw(ANA_VLANTIDX_VLAN_PGID_CPU_DIS_SET(cpu_dis) | 41 lan_rmw(ANA_VLAN_PORT_MASK_VLAN_PORT_MASK_SET(mask), 46 lan_rmw(ANA_VLANACCESS_VLAN_TBL_CMD_SET(VLANACCESS_CMD_WRITE), 167 lan_rmw(val, 172 lan_rmw(DEV_MAC_TAGS_CFG_VLAN_AWR_ENA_SET(port->vlan_aware) | 201 lan_rmw(val, 206 lan_rmw(REW_PORT_VLAN_CFG_PORT_TPID_SET(ETH_P_8021Q) | 288 lan_rmw(ANA_VLANACCESS_VLAN_TBL_CMD_SET(VLANACCESS_CMD_INIT),
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H A D | lan966x_taprio.c | 60 lan_rmw(QSYS_TAS_CFG_CTRL_LIST_NUM_SET(list), 72 lan_rmw(QSYS_TAS_LST_LIST_STATE_SET(state), 296 lan_rmw(QSYS_TAS_CFG_CTRL_GCL_ENTRY_NUM_SET(next), 339 lan_rmw(QSYS_TAS_CFG_CTRL_LIST_NUM_SET(list), 345 lan_rmw(QSYS_TAS_LIST_CFG_LIST_BASE_ADDR_SET(base), 352 lan_rmw(QSYS_TAS_CFG_CTRL_GCL_ENTRY_NUM_SET(next), 434 lan_rmw(QSYS_TAS_PROFILE_CFG_LINK_SPEED_SET(taprio_speed), 476 lan_rmw(QSYS_TAS_STARTUP_CFG_OBSOLETE_IDX_SET(obs_list), 481 lan_rmw(QSYS_TAS_LST_LIST_STATE_SET(LAN966X_TAPRIO_STATE_ADVANCING), 506 lan_rmw(QSYS_TAS_CFG_CTRL_LIST_NUM_MAX_SE [all...] |
H A D | lan966x_tbf.c | 42 lan_rmw(QSYS_SE_CFG_SE_AVB_ENA_SET(0) | 74 lan_rmw(QSYS_SE_CFG_SE_AVB_ENA_SET(0) |
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H A D | lan966x_ets.c | 68 lan_rmw(QSYS_SE_CFG_SE_DWRR_CNT_SET(count) | 89 lan_rmw(QSYS_SE_CFG_SE_DWRR_CNT_SET(0) |
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H A D | lan966x_mirror.c | 47 lan_rmw(ANA_PORT_CFG_SRC_MIRROR_ENA_SET(1), 80 lan_rmw(ANA_PORT_CFG_SRC_MIRROR_ENA_SET(0),
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H A D | lan966x_ptp.c | 432 lan_rmw(PTP_PIN_CFG_PIN_ACTION_SET(PTP_PIN_ACTION_SAVE) | 490 lan_rmw(PTP_TWOSTEP_CTRL_NXT_SET(1), 515 lan_rmw(PTP_TWOSTEP_CTRL_NXT_SET(1), 625 lan_rmw(PTP_DOM_CFG_CLKCFG_DIS_SET(1 << BIT(phc->index)), 634 lan_rmw(PTP_DOM_CFG_CLKCFG_DIS_SET(0), 653 lan_rmw(PTP_PIN_CFG_PIN_ACTION_SET(PTP_PIN_ACTION_IDLE) | 669 lan_rmw(PTP_PIN_CFG_PIN_ACTION_SET(PTP_PIN_ACTION_LOAD) | 692 lan_rmw(PTP_PIN_CFG_PIN_ACTION_SET(PTP_PIN_ACTION_SAVE) | 730 lan_rmw(PTP_PIN_CFG_PIN_ACTION_SET(PTP_PIN_ACTION_IDLE) | 742 lan_rmw(PTP_PIN_CFG_PIN_ACTION_SE [all...] |
H A D | lan966x_fdma.c | 187 lan_rmw(FDMA_PORT_CTRL_XTR_STOP_SET(0), 195 lan_rmw(FDMA_INTR_DB_ENA_INTR_DB_ENA_SET(mask), 200 lan_rmw(FDMA_CH_ACTIVATE_CH_ACTIVATE_SET(BIT(rx->channel_id)), 211 lan_rmw(FDMA_CH_DISABLE_CH_DISABLE_SET(BIT(rx->channel_id)), 219 lan_rmw(FDMA_CH_DB_DISCARD_DB_DISCARD_SET(BIT(rx->channel_id)), 228 lan_rmw(FDMA_CH_RELOAD_CH_RELOAD_SET(BIT(rx->channel_id)), 312 lan_rmw(FDMA_PORT_CTRL_INJ_STOP_SET(0), 320 lan_rmw(FDMA_INTR_DB_ENA_INTR_DB_ENA_SET(mask), 325 lan_rmw(FDMA_CH_ACTIVATE_CH_ACTIVATE_SET(BIT(tx->channel_id)), 336 lan_rmw(FDMA_CH_DISABLE_CH_DISABLE_SE [all...] |
H A D | lan966x_switchdev.c | 36 lan_rmw(ANA_PGID_PGID_SET(flood_mask_ip), 52 lan_rmw(ANA_PGID_PGID_SET(val), 73 lan_rmw(ANA_PGID_PGID_SET(val), 89 lan_rmw(ANA_PGID_PGID_SET(val), 96 lan_rmw(ANA_PORT_CFG_LEARN_ENA_SET(enabled), 170 lan_rmw(ANA_PORT_CFG_LEARN_ENA_SET(learn_ena), 196 lan_rmw(ANA_CPU_FWD_CFG_IGMP_REDIR_ENA_SET(mcast_ena) |
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H A D | lan966x_main.c | 178 lan_rmw(ANA_PORT_CFG_LEARNAUTO_SET(1) | 910 lan_rmw(ANA_ADVLEARN_VLAN_CHK_SET(1), 934 lan_rmw(QS_INJ_CTRL_GAP_SIZE_SET(0), 952 lan_rmw(ANA_FLOODING_FLD_MULTICAST_SET(PGID_MC) | 962 lan_rmw(ANA_PGID_CFG_OBEY_VLAN_SET(1), 968 lan_rmw(ANA_PGID_PGID_SET(0x0), 991 lan_rmw(ANA_PGID_PGID_SET(0), 994 lan_rmw(ANA_PGID_PGID_SET(BIT(CPU_PORT)), 999 lan_rmw(GENMASK(lan966x->num_phys_ports - 1, 0), 1004 lan_rmw(GENMAS [all...] |
H A D | lan966x_phylink.c | 78 lan_rmw(DEV_CLOCK_CFG_PCS_RX_RST_SET(0) |
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H A D | lan966x_police.c | 162 lan_rmw(ANA_POL_CFG_PORT_POL_ENA_SET(1) | 195 lan_rmw(ANA_POL_CFG_PORT_POL_ENA_SET(0) |
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H A D | lan966x_mdb.c | 289 lan_rmw(ANA_PGID_PGID_SET(mdb_entry->ports), 346 lan_rmw(ANA_PGID_PGID_SET(mdb_entry->ports), 428 lan_rmw(ANA_PGID_PGID_SET(mdb_entry->ports), 483 lan_rmw(ANA_PGID_PGID_SET(mdb_entry->ports),
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H A D | lan966x_vcap_impl.c | 684 lan_rmw(ANA_VCAP_CFG_S1_ENA_SET(true), 697 lan_rmw(REW_PORT_CFG_ES0_EN_SET(false), 743 lan_rmw(ANA_VCAP_S2_CFG_ENA_SET(true), 747 lan_rmw(ANA_VCAP_CFG_S1_ENA_SET(true), 751 lan_rmw(REW_PORT_CFG_ES0_EN_SET(true), 758 lan_rmw(REW_STAT_CFG_STAT_MODE_SET(1),
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H A D | lan966x_mac.c | 188 lan_rmw(ANA_AUTOAGE_AGE_PERIOD_SET(ageing / 2), 544 lan_rmw(ANA_MACACCESS_MAC_TABLE_CMD_SET(MACACCESS_CMD_SYNC_GET_NEXT), 587 lan_rmw(ANA_ANAINTR_INTR_SET(0),
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H A D | lan966x_lag.c | 111 lan_rmw(ANA_PORT_CFG_PORTID_VAL_SET(lag_id),
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H A D | lan966x_main.h | 778 static inline void lan_rmw(u32 val, u32 mask, struct lan966x *lan966x, function
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/linux-master/drivers/phy/microchip/ |
H A D | lan966x_serdes.c | 26 #define lan_rmw(val, mask, reg, off) \ macro 189 lan_rmw(HSIO_SD_CFG_LANE_10BIT_SEL_SET(res_struct->lane_10bit_sel) | 207 lan_rmw(HSIO_MPLL_CFG_MPLL_MULTIPLIER_SET(res_struct->mpll_multiplier) | 213 lan_rmw(HSIO_SD_CFG_RX_TERM_EN_SET(res_struct->rx_term_en), 217 lan_rmw(HSIO_MPLL_CFG_REF_SSP_EN_SET(1), 223 lan_rmw(HSIO_SD_CFG_PHY_RESET_SET(0), 229 lan_rmw(HSIO_MPLL_CFG_MPLL_EN_SET(1), 244 lan_rmw(HSIO_SD_CFG_TX_CM_EN_SET(1), 259 lan_rmw(HSIO_SD_CFG_RX_PLL_EN_SET(1) | 287 lan_rmw(HSIO_SD_CFG_TX_DATA_EN_SE [all...] |