Searched refs:ixLCAC_MC0_OVR_SEL (Results 1 - 9 of 9) sorted by path

/linux-master/drivers/gpu/drm/amd/include/asic_reg/smu/
H A Dsmu_6_0_d.h27 #define ixLCAC_MC0_OVR_SEL 0x011D macro
H A Dsmu_7_0_0_d.h726 #define ixLCAC_MC0_OVR_SEL 0xc0400d34 macro
H A Dsmu_7_1_0_d.h1245 #define ixLCAC_MC0_OVR_SEL 0xc0400d34 macro
H A Dsmu_7_1_1_d.h1026 #define ixLCAC_MC0_OVR_SEL 0xc0400134 macro
H A Dsmu_8_0_d.h633 #define ixLCAC_MC0_OVR_SEL 0xd0208134 macro
H A Dsmu_7_0_1_d.h1216 #define ixLCAC_MC0_OVR_SEL 0xc0400d34 macro
H A Dsmu_7_1_2_d.h1177 #define ixLCAC_MC0_OVR_SEL 0xc0400134 macro
H A Dsmu_7_1_3_d.h1109 #define ixLCAC_MC0_OVR_SEL 0xc0400134 macro
/linux-master/drivers/gpu/drm/amd/pm/legacy-dpm/
H A Dkv_dpm.c526 WREG32_SMC(ixLCAC_MC0_OVR_SEL, 0);

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