Searched refs:irq_enable_mask (Results 1 - 9 of 9) sorted by relevance

/linux-master/drivers/gpu/drm/i915/gt/
H A Dgen2_engine_cs.c297 i915->irq_mask &= ~engine->irq_enable_mask;
306 i915->irq_mask |= engine->irq_enable_mask;
312 engine->i915->irq_mask &= ~engine->irq_enable_mask;
319 engine->i915->irq_mask |= engine->irq_enable_mask;
325 gen5_gt_enable_irq(engine->gt, engine->irq_enable_mask);
330 gen5_gt_disable_irq(engine->gt, engine->irq_enable_mask);
H A Dgen6_engine_cs.c428 ~(engine->irq_enable_mask | engine->irq_keep_mask));
433 gen5_gt_enable_irq(engine->gt, engine->irq_enable_mask);
439 gen5_gt_disable_irq(engine->gt, engine->irq_enable_mask);
444 ENGINE_WRITE(engine, RING_IMR, ~engine->irq_enable_mask);
449 gen6_gt_pm_unmask_irq(engine->gt, engine->irq_enable_mask);
455 gen6_gt_pm_mask_irq(engine->gt, engine->irq_enable_mask);
H A Dintel_ring_submission.c1170 engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
1185 engine->irq_enable_mask = I915_USER_INTERRUPT;
1201 engine->irq_enable_mask = GT_BSD_USER_INTERRUPT;
1210 engine->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
1212 engine->irq_enable_mask = I915_BSD_USER_INTERRUPT;
1221 engine->irq_enable_mask = GT_BLT_USER_INTERRUPT;
1236 engine->irq_enable_mask = PM_VEBOX_USER_INTERRUPT;
H A Dintel_engine_types.h500 u32 irq_enable_mask; /* bitmask to enable ring interrupt */ member in struct:intel_engine_cs
H A Dintel_execlists_submission.c3262 ~(engine->irq_enable_mask | engine->irq_keep_mask));
3516 engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT << shift;
/linux-master/arch/mips/sgi-ip27/
H A Dip27-irq.c35 static DEFINE_PER_CPU(unsigned long [2], irq_enable_mask);
55 unsigned long *mask = per_cpu(irq_enable_mask, hd->cpu);
65 unsigned long *mask = per_cpu(irq_enable_mask, hd->cpu);
192 unsigned long *mask = per_cpu(irq_enable_mask, cpu);
232 unsigned long *mask = per_cpu(irq_enable_mask, cpu);
255 unsigned long *mask = per_cpu(irq_enable_mask, cpu);
/linux-master/arch/mips/sgi-ip30/
H A Dip30-irq.c27 static DEFINE_PER_CPU(unsigned long, irq_enable_mask);
147 unsigned long *mask = &per_cpu(irq_enable_mask, hd->cpu);
156 unsigned long *mask = &per_cpu(irq_enable_mask, hd->cpu);
166 unsigned long *mask = &per_cpu(irq_enable_mask, hd->cpu);
250 unsigned long *mask = &per_cpu(irq_enable_mask, cpu);
281 mask = &per_cpu(irq_enable_mask, 0);
284 mask = &per_cpu(irq_enable_mask, 1);
/linux-master/drivers/pinctrl/
H A Dpinctrl-single.c133 * @irq_enable_mask: optional SoC specific interrupt enable mask
140 unsigned irq_enable_mask; member in struct:pcs_soc_data
697 if (pcs_soc->irq_enable_mask) {
701 if (val & pcs_soc->irq_enable_mask) {
704 val &= ~pcs_soc->irq_enable_mask;
1408 soc_mask = pcs_soc->irq_enable_mask;
1579 if (!pcs_soc->irq_enable_mask ||
1937 .irq_enable_mask = (1 << 14), /* OMAP_WAKEUP_EN */
1942 .irq_enable_mask = (1 << 24), /* WAKEUPENABLE */
1948 .irq_enable_mask
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/linux-master/drivers/dma/ti/
H A Domap-dma.c59 uint32_t irq_enable_mask; member in struct:omap_dmadev
639 status &= od->irq_enable_mask;
732 od->irq_enable_mask |= val;
733 omap_dma_glbl_write(od, IRQENABLE_L1, od->irq_enable_mask);
767 od->irq_enable_mask &= ~BIT(c->dma_ch);
768 omap_dma_glbl_write(od, IRQENABLE_L1, od->irq_enable_mask);
1777 od->irq_enable_mask = 0;

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