Searched refs:iq_no (Results 1 - 18 of 18) sorted by relevance

/linux-master/drivers/net/ethernet/cavium/liquidio/
H A Drequest_manager.c39 static void __check_db_timeout(struct octeon_device *oct, u64 iq_no);
53 u32 iq_no = (u32)txpciq.s.q_no; local
73 iq = oct->instr_queue[iq_no];
80 iq_no);
96 iq_no);
101 iq_no, iq->base_addr, &iq->base_addr_dma, iq->max_count);
117 if (iq_no == 0) {
126 oct->io_qmask.iq |= BIT_ULL(iq_no);
129 oct->io_qmask.iq64B |= ((conf->instr_type == 64) << iq_no);
132 oct->fn_list.setup_iq_regs(oct, iq_no);
156 octeon_delete_instr_queue(struct octeon_device *oct, u32 iq_no) argument
198 u32 iq_no = (u32)txpciq.s.q_no; local
277 octeon_ring_doorbell_locked(struct octeon_device *oct, u32 iq_no) argument
493 __check_db_timeout(struct octeon_device *oct, u64 iq_no) argument
527 u64 iq_no = wk->ctxul; local
536 octeon_send_command(struct octeon_device *oct, u32 iq_no, u32 force_db, void *cmd, void *buf, u32 datasize, u32 reqtype) argument
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H A Docteon_iq.h296 u32 iq_no; member in struct:octeon_soft_command
324 #define INCR_INSTRQUEUE_PKT_COUNT(octeon_dev_ptr, iq_no, field, count) \
325 (((octeon_dev_ptr)->instr_queue[iq_no]->stats.field) += count)
355 * @param iq_no - queue to be deleted (0 <= q_no <= 3).
362 int octeon_delete_instr_queue(struct octeon_device *octeon_dev, u32 iq_no);
367 octeon_ring_doorbell_locked(struct octeon_device *oct, u32 iq_no);
377 int octeon_send_command(struct octeon_device *oct, u32 iq_no,
394 int q_index, union oct_txpciq iq_no, u32 num_descs,
H A Docteon_nic.h53 u64 iq_no; member in struct:octnic_ctrl_pkt
94 u32 iq_no:8; member in struct:octnic_cmd_setup::__anon5578
140 port = (int)oct->instr_queue[setup->s.iq_no]->txpciq.s.port;
191 ih3->pkind = oct->instr_queue[setup->s.iq_no]->txpciq.s.pkind;
206 pki_ih3->uqpg = oct->instr_queue[setup->s.iq_no]->txpciq.s.use_qpg;
208 port = (int)oct->instr_queue[setup->s.iq_no]->txpciq.s.port;
216 pki_ih3->qpg = oct->instr_queue[setup->s.iq_no]->txpciq.s.qpg;
H A Dcn66xx_device.c264 void lio_cn6xxx_setup_iq_regs(struct octeon_device *oct, u32 iq_no) argument
266 struct octeon_instr_queue *iq = oct->instr_queue[iq_no];
268 octeon_write_csr64(oct, CN6XXX_SLI_IQ_PKT_INSTR_HDR64(iq_no), 0);
271 octeon_write_csr64(oct, CN6XXX_SLI_IQ_BASE_ADDR64(iq_no),
273 octeon_write_csr(oct, CN6XXX_SLI_IQ_SIZE(iq_no), iq->max_count);
278 iq->doorbell_reg = oct->mmio[0].hw_addr + CN6XXX_SLI_IQ_DOORBELL(iq_no);
280 + CN6XXX_SLI_IQ_INSTR_COUNT(iq_no);
282 iq_no, iq->doorbell_reg, iq->inst_cnt_reg);
290 static void lio_cn66xx_setup_iq_regs(struct octeon_device *oct, u32 iq_no) argument
292 lio_cn6xxx_setup_iq_regs(oct, iq_no);
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H A Docteon_nic.c127 sc->iq_no = (u32)nctrl->iq_no;
H A Dcn66xx_device.h76 void lio_cn6xxx_setup_iq_regs(struct octeon_device *oct, u32 iq_no);
H A Dcn23xx_vf_device.c212 static void cn23xx_setup_vf_iq_regs(struct octeon_device *oct, u32 iq_no) argument
214 struct octeon_instr_queue *iq = oct->instr_queue[iq_no];
218 octeon_write_csr64(oct, CN23XX_VF_SLI_IQ_BASE_ADDR64(iq_no),
220 octeon_write_csr(oct, CN23XX_VF_SLI_IQ_SIZE(iq_no), iq->max_count);
226 (u8 *)oct->mmio[0].hw_addr + CN23XX_VF_SLI_IQ_DOORBELL(iq_no);
228 (u8 *)oct->mmio[0].hw_addr + CN23XX_VF_SLI_IQ_INSTR_COUNT64(iq_no);
230 iq_no, iq->doorbell_reg, iq->inst_cnt_reg);
H A Dlio_vf_rep.c81 sc->iq_no = 0;
354 u32 iq_no; local
359 iq_no = sc->iq_no;
362 if (octnet_iq_is_full(oct, iq_no))
417 sc->iq_no = parent_lio->txq;
H A Dlio_vf_main.c622 sc->iq_no = lio->linfo.txpciq[0].s.q_no;
1054 nctrl.iq_no = lio->linfo.txpciq[0].s.q_no;
1103 nctrl.iq_no = lio->linfo.txpciq[0].s.q_no;
1146 nctrl.iq_no = lio->linfo.txpciq[0].s.q_no;
1180 int i, iq_no, oq_no; local
1188 iq_no = lio->linfo.txpciq[i].s.q_no;
1189 iq_stats = &oct->instr_queue[iq_no]->stats;
1379 sc->iq_no = ndata->q_no;
1385 retval = octeon_send_command(oct, sc->iq_no, ring_doorbell, &sc->cmd,
1414 int q_idx = 0, iq_no local
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H A Dlio_core.c176 nctrl.iq_no = lio->linfo.txpciq[0].s.q_no;
756 int tx_done = 0, iq_no; local
761 iq_no = droq->q_no;
767 iq = oct->instr_queue[iq_no];
781 lio_update_txq_status(oct, iq_no);
784 __func__, iq_no);
1242 sc->iq_no = lio->linfo.txpciq[0].s.q_no;
1423 sc->iq_no = lio->linfo.txpciq[0].s.q_no;
1498 sc->iq_no = lio->linfo.txpciq[0].s.q_no;
1565 sc->iq_no
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H A Dlio_main.c636 sc->iq_no = lio->linfo.txpciq[0].s.q_no;
1174 sc->iq_no = lio->linfo.txpciq[0].s.q_no;
1968 nctrl.iq_no = lio->linfo.txpciq[0].s.q_no;
2016 nctrl.iq_no = lio->linfo.txpciq[0].s.q_no;
2051 int i, iq_no, oq_no; local
2059 iq_no = lio->linfo.txpciq[i].s.q_no;
2060 iq_stats = &oct->instr_queue[iq_no]->stats;
2269 sc->iq_no = ndata->q_no;
2280 retval = octeon_send_command(oct, sc->iq_no, ring_doorbell, &sc->cmd,
2313 int q_idx = 0, iq_no local
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H A Dcn23xx_pf_device.c587 static void cn23xx_setup_iq_regs(struct octeon_device *oct, u32 iq_no) argument
589 struct octeon_instr_queue *iq = oct->instr_queue[iq_no];
592 iq_no += oct->sriov_info.pf_srn;
595 octeon_write_csr64(oct, CN23XX_SLI_IQ_BASE_ADDR64(iq_no),
597 octeon_write_csr(oct, CN23XX_SLI_IQ_SIZE(iq_no), iq->max_count);
603 (u8 *)oct->mmio[0].hw_addr + CN23XX_SLI_IQ_DOORBELL(iq_no);
605 (u8 *)oct->mmio[0].hw_addr + CN23XX_SLI_IQ_INSTR_COUNT64(iq_no);
607 iq_no, iq->doorbell_reg, iq->inst_cnt_reg);
H A Dlio_ethtool.c483 nctrl.iq_no = lio->linfo.txpciq[0].s.q_no;
718 nctrl.iq_no = lio->linfo.txpciq[0].s.q_no;
744 nctrl.iq_no = lio->linfo.txpciq[0].s.q_no;
787 sc->iq_no = lio->linfo.txpciq[0].s.q_no;
1026 sc->iq_no = 0;
1397 nctrl.iq_no = lio->linfo.txpciq[0].s.q_no;
1446 /*sum of oct->instr_queue[iq_no]->stats.tx_done */
1450 /*sum of oct->instr_queue[iq_no]->stats.tx_tot_bytes */
1470 /*sum of oct->instr_queue[iq_no]->stats.tx_dropped */
1735 /* sum of oct->instr_queue[iq_no]
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H A Docteon_device.c875 u32 iq_no = 0; local
901 txpciq.s.q_no = iq_no;
/linux-master/drivers/net/ethernet/marvell/octeon_ep_vf/
H A Doctep_vf_cn9k.c161 static void octep_vf_setup_iq_regs_cn93(struct octep_vf_device *oct, int iq_no) argument
163 struct octep_vf_iq *iq = oct->iq[iq_no];
167 reg_val = octep_vf_read_csr64(oct, CN93_VF_SDP_R_IN_CONTROL(iq_no));
172 reg_val = octep_vf_read_csr64(oct, CN93_VF_SDP_R_IN_CONTROL(iq_no));
178 octep_vf_write_csr64(oct, CN93_VF_SDP_R_IN_CONTROL(iq_no), reg_val);
181 octep_vf_write_csr64(oct, CN93_VF_SDP_R_IN_INSTR_BADDR(iq_no), iq->desc_ring_dma);
182 octep_vf_write_csr64(oct, CN93_VF_SDP_R_IN_INSTR_RSIZE(iq_no), iq->max_count);
185 iq->doorbell_reg = oct->mmio.hw_addr + CN93_VF_SDP_R_IN_INSTR_DBELL(iq_no);
186 iq->inst_cnt_reg = oct->mmio.hw_addr + CN93_VF_SDP_R_IN_CNTS(iq_no);
187 iq->intr_lvl_reg = oct->mmio.hw_addr + CN93_VF_SDP_R_IN_INT_LEVELS(iq_no);
366 octep_vf_enable_iq_cn93(struct octep_vf_device *oct, int iq_no) argument
415 octep_vf_disable_iq_cn93(struct octep_vf_device *oct, int iq_no) argument
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H A Doctep_vf_cnxk.c164 static void octep_vf_setup_iq_regs_cnxk(struct octep_vf_device *oct, int iq_no) argument
166 struct octep_vf_iq *iq = oct->iq[iq_no];
170 reg_val = octep_vf_read_csr64(oct, CNXK_VF_SDP_R_IN_CONTROL(iq_no));
175 reg_val = octep_vf_read_csr64(oct, CNXK_VF_SDP_R_IN_CONTROL(iq_no));
181 octep_vf_write_csr64(oct, CNXK_VF_SDP_R_IN_CONTROL(iq_no), reg_val);
184 octep_vf_write_csr64(oct, CNXK_VF_SDP_R_IN_INSTR_BADDR(iq_no), iq->desc_ring_dma);
185 octep_vf_write_csr64(oct, CNXK_VF_SDP_R_IN_INSTR_RSIZE(iq_no), iq->max_count);
188 iq->doorbell_reg = oct->mmio.hw_addr + CNXK_VF_SDP_R_IN_INSTR_DBELL(iq_no);
189 iq->inst_cnt_reg = oct->mmio.hw_addr + CNXK_VF_SDP_R_IN_CNTS(iq_no);
190 iq->intr_lvl_reg = oct->mmio.hw_addr + CNXK_VF_SDP_R_IN_INT_LEVELS(iq_no);
377 octep_vf_enable_iq_cnxk(struct octep_vf_device *oct, int iq_no) argument
426 octep_vf_disable_iq_cnxk(struct octep_vf_device *oct, int iq_no) argument
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/linux-master/drivers/net/ethernet/marvell/octeon_ep/
H A Doctep_cn9k_pf.c263 static void octep_setup_iq_regs_cn93_pf(struct octep_device *oct, int iq_no) argument
265 struct octep_iq *iq = oct->iq[iq_no];
269 iq_no += CFG_GET_PORTS_PF_SRN(oct->conf);
270 reg_val = octep_read_csr64(oct, CN93_SDP_R_IN_CONTROL(iq_no));
275 reg_val = octep_read_csr64(oct, CN93_SDP_R_IN_CONTROL(iq_no));
282 octep_write_csr64(oct, CN93_SDP_R_IN_CONTROL(iq_no), reg_val);
285 octep_write_csr64(oct, CN93_SDP_R_IN_INSTR_BADDR(iq_no),
287 octep_write_csr64(oct, CN93_SDP_R_IN_INSTR_RSIZE(iq_no),
294 CN93_SDP_R_IN_INSTR_DBELL(iq_no);
296 CN93_SDP_R_IN_CNTS(iq_no);
739 octep_enable_iq_cn93_pf(struct octep_device *oct, int iq_no) argument
792 octep_disable_iq_cn93_pf(struct octep_device *oct, int iq_no) argument
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H A Doctep_cnxk_pf.c283 static void octep_setup_iq_regs_cnxk_pf(struct octep_device *oct, int iq_no) argument
285 struct octep_iq *iq = oct->iq[iq_no];
289 iq_no += CFG_GET_PORTS_PF_SRN(oct->conf);
290 reg_val = octep_read_csr64(oct, CNXK_SDP_R_IN_CONTROL(iq_no));
295 reg_val = octep_read_csr64(oct, CNXK_SDP_R_IN_CONTROL(iq_no));
302 octep_write_csr64(oct, CNXK_SDP_R_IN_CONTROL(iq_no), reg_val);
305 octep_write_csr64(oct, CNXK_SDP_R_IN_INSTR_BADDR(iq_no),
307 octep_write_csr64(oct, CNXK_SDP_R_IN_INSTR_RSIZE(iq_no),
314 CNXK_SDP_R_IN_INSTR_DBELL(iq_no);
316 CNXK_SDP_R_IN_CNTS(iq_no);
762 octep_enable_iq_cnxk_pf(struct octep_device *oct, int iq_no) argument
815 octep_disable_iq_cnxk_pf(struct octep_device *oct, int iq_no) argument
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