Searched refs:iobase (Results 1 - 25 of 284) sorted by relevance

1234567891011>>

/linux-master/drivers/comedi/drivers/
H A Daddi_watchdog.h7 void addi_watchdog_reset(unsigned long iobase);
8 int addi_watchdog_init(struct comedi_subdevice *s, unsigned long iobase);
H A D8255.c50 unsigned long iobase; local
55 iobase = it->options[i];
56 if (!iobase)
70 iobase = it->options[i];
73 * __comedi_request_region() does not set dev->iobase.
76 * comedi_config, the 'iobase' is the actual I/O port
79 ret = __comedi_request_region(dev, iobase, I8255_SIZE);
83 ret = subdev_8255_io_init(dev, s, iobase);
89 release_region(iobase, I8255_SIZE);
H A Ddt2817.c65 outb(oe, dev->iobase + DT2817_CR);
75 unsigned long iobase = dev->iobase + DT2817_DATA; local
82 outb(s->state & 0xff, iobase + 0);
84 outb((s->state >> 8) & 0xff, iobase + 1);
86 outb((s->state >> 16) & 0xff, iobase + 2);
88 outb((s->state >> 24) & 0xff, iobase + 3);
91 val = inb(iobase + 0);
92 val |= (inb(iobase + 1) << 8);
93 val |= (inb(iobase
[all...]
H A Dni_atmio16d.c152 outw(0xFFC2, dev->iobase + AM9513A_COM_REG);
153 outw(0xFF02, dev->iobase + AM9513A_COM_REG);
154 outw(0x4, dev->iobase + AM9513A_DATA_REG);
155 outw(0xFF0A, dev->iobase + AM9513A_COM_REG);
156 outw(0x3, dev->iobase + AM9513A_DATA_REG);
157 outw(0xFF42, dev->iobase + AM9513A_COM_REG);
158 outw(0xFF42, dev->iobase + AM9513A_COM_REG);
160 outw(0xFFC4, dev->iobase + AM9513A_COM_REG);
161 outw(0xFF03, dev->iobase + AM9513A_COM_REG);
162 outw(0x4, dev->iobase
[all...]
H A Daddi_watchdog.c18 unsigned long iobase; member in struct:addi_watchdog_private
44 outl(reload, spriv->iobase + ADDI_TCW_RELOAD_REG);
57 outl(spriv->wdog_ctrl, spriv->iobase + ADDI_TCW_CTRL_REG);
71 data[i] = inl(spriv->iobase + ADDI_TCW_STATUS_REG);
92 spriv->iobase + ADDI_TCW_CTRL_REG);
98 void addi_watchdog_reset(unsigned long iobase) argument
100 outl(0x0, iobase + ADDI_TCW_CTRL_REG);
101 outl(0x0, iobase + ADDI_TCW_RELOAD_REG);
105 int addi_watchdog_init(struct comedi_subdevice *s, unsigned long iobase) argument
113 spriv->iobase
[all...]
H A Dpcl724.c80 unsigned long iobase)
82 int movport = I8255_SIZE * (iobase >> 12);
84 iobase &= 0x0fff;
86 outb(port + movport, iobase);
88 outb(data, iobase + 1);
91 return inb(iobase + 1);
99 unsigned long iobase; local
126 iobase = dev->iobase + (i * 0x1000);
128 iobase);
78 pcl724_8255mapped_io(struct comedi_device *dev, int dir, int port, int data, unsigned long iobase) argument
[all...]
H A Dni_daq_700.c84 outb(s->state & 0xff, dev->iobase + DIO_W);
88 val |= inb(dev->iobase + DIO_R) << 8;
119 status = inb(dev->iobase + STA_R2);
122 status = inb(dev->iobase + STA_R1);
148 outb(r3_bits | (range & 0x03), dev->iobase + CMD_R3);
152 outb(chan | 0x80, dev->iobase + CMD_R1);
159 outb(0x00, dev->iobase + CMD_R2); /* enable ADC conversions */
160 outb(0x30, dev->iobase + CMO_R); /* mode 0 out0 L, from H */
161 outb(0x00, dev->iobase + ADCLEAR_R); /* clear the ADC FIFO */
163 inw(dev->iobase
197 unsigned long iobase = dev->iobase; local
[all...]
H A Daddi_apci_1564.c117 * dev->iobase Register Map
175 outl(0x0, dev->iobase + APCI1564_DI_IRQ_REG);
176 inl(dev->iobase + APCI1564_DI_INT_STATUS_REG);
177 outl(0x0, dev->iobase + APCI1564_DI_INT_MODE1_REG);
178 outl(0x0, dev->iobase + APCI1564_DI_INT_MODE2_REG);
181 outl(0x0, dev->iobase + APCI1564_DO_REG);
182 outl(0x0, dev->iobase + APCI1564_DO_INT_CTRL_REG);
185 addi_watchdog_reset(dev->iobase + APCI1564_WDOG_IOBASE);
192 unsigned long iobase = devpriv->counters + ADDI_TCW_CTRL_REG; local
195 outl(0x0, iobase
239 unsigned long iobase; local
579 unsigned long iobase = devpriv->counters + APCI1564_COUNTER(chan); local
629 unsigned long iobase = devpriv->counters + APCI1564_COUNTER(chan); local
648 unsigned long iobase = devpriv->counters + APCI1564_COUNTER(chan); local
[all...]
H A Daddi_apci_3501.c100 status = inl(dev->iobase + APCI3501_AO_CTRL_STATUS_REG);
124 outl(0, dev->iobase + APCI3501_AO_CTRL_STATUS_REG);
128 dev->iobase + APCI3501_AO_CTRL_STATUS_REG);
147 dev->iobase + APCI3501_AO_DATA_REG);
160 data[1] = inl(dev->iobase + APCI3501_DI_REG) & 0x3;
170 s->state = inl(dev->iobase + APCI3501_DO_REG);
173 outl(s->state, dev->iobase + APCI3501_DO_REG);
180 static void apci3501_eeprom_wait(unsigned long iobase) argument
185 val = inb(iobase + AMCC_OP_REG_MCSR_NVCMD);
189 static unsigned short apci3501_eeprom_readw(unsigned long iobase, argument
[all...]
H A Daddi_apci_2200.c33 data[1] = inw(dev->iobase + APCI2200_DI_REG);
43 s->state = inw(dev->iobase + APCI2200_DO_REG);
46 outw(s->state, dev->iobase + APCI2200_DO_REG);
55 outw(0x0, dev->iobase + APCI2200_DO_REG);
57 addi_watchdog_reset(dev->iobase + APCI2200_WDOG_REG);
73 dev->iobase = pci_resource_start(pcidev, 1);
99 ret = addi_watchdog_init(s, dev->iobase + APCI2200_WDOG_REG);
109 if (dev->iobase)
H A Dpcmmio.c188 unsigned long iobase = dev->iobase; local
194 outb(val & 0xff, iobase + PCMMIO_PORT_REG(port + 0));
195 outb((val >> 8) & 0xff, iobase + PCMMIO_PORT_REG(port + 1));
196 outb((val >> 16) & 0xff, iobase + PCMMIO_PORT_REG(port + 2));
198 outb(PCMMIO_PAGE(page), iobase + PCMMIO_PAGE_LOCK_REG);
199 outb(val & 0xff, iobase + PCMMIO_PAGE_REG(0));
200 outb((val >> 8) & 0xff, iobase + PCMMIO_PAGE_REG(1));
201 outb((val >> 16) & 0xff, iobase + PCMMIO_PAGE_REG(2));
210 unsigned long iobase local
534 unsigned long iobase = dev->iobase; local
617 unsigned long iobase = dev->iobase; local
[all...]
H A Ddmm32at.c166 outb(DMM32AT_FIFO_CTRL_FIFORST, dev->iobase + DMM32AT_FIFO_CTRL_REG);
170 dev->iobase + DMM32AT_FIFO_CTRL_REG);
172 outb(chan, dev->iobase + DMM32AT_AI_LO_CHAN_REG);
173 outb(last_chan, dev->iobase + DMM32AT_AI_HI_CHAN_REG);
174 outb(dmm32at_rangebits[range], dev->iobase + DMM32AT_AI_CFG_REG);
182 val = inb(dev->iobase + DMM32AT_AI_LSB_REG);
183 val |= (inb(dev->iobase + DMM32AT_AI_MSB_REG) << 8);
196 status = inb(dev->iobase + context);
219 outb(0xff, dev->iobase + DMM32AT_AI_START_CONV_REG);
343 outb(0, dev->iobase
[all...]
H A Damplc_pc236.h30 int amplc_pc236_common_attach(struct comedi_device *dev, unsigned long iobase,
H A Damplc_pc263.c50 outb(s->state & 0xff, dev->iobase + PC263_DO_0_7_REG);
51 outb((s->state >> 8) & 0xff, dev->iobase + PC263_DO_8_15_REG);
82 s->state = inb(dev->iobase + PC263_DO_0_7_REG) |
83 (inb(dev->iobase + PC263_DO_8_15_REG) << 8);
H A Dfl512.c58 outb(chan, dev->iobase + FL512_AI_MUX_REG);
61 outb(0, dev->iobase + FL512_AI_START_CONV_REG);
66 val = inb(dev->iobase + FL512_AI_LSB_REG);
67 val |= (inb(dev->iobase + FL512_AI_MSB_REG) << 8);
89 outb(val & 0x0ff, dev->iobase + FL512_AO_DATA_REG(chan));
90 outb((val >> 8) & 0xf, dev->iobase + FL512_AO_DATA_REG(chan));
91 inb(dev->iobase + FL512_AO_TRIG_REG(chan));
/linux-master/drivers/staging/vt6655/
H A Dsrom.c51 * iobase - I/O base address
59 unsigned char SROMbyReadEmbedded(void __iomem *iobase, argument
68 byOrg = ioread8(iobase + MAC_REG_I2MCFG);
70 iowrite8(byOrg & (~I2MCFG_NORETRY), iobase + MAC_REG_I2MCFG);
72 iowrite8(EEP_I2C_DEV_ID, iobase + MAC_REG_I2MTGID);
73 iowrite8(contnt_offset, iobase + MAC_REG_I2MTGAD);
76 iowrite8(I2MCSR_EEMR, iobase + MAC_REG_I2MCSR);
79 byWait = ioread8(iobase + MAC_REG_I2MCSR);
89 byData = ioread8(iobase + MAC_REG_I2MDIPT);
90 iowrite8(byOrg, iobase
106 SROMvReadAllContents(void __iomem *iobase, unsigned char *pbyEepromRegs) argument
130 SROMvReadEtherAddress(void __iomem *iobase, unsigned char *pbyEtherAddress) argument
[all...]
/linux-master/drivers/irqchip/
H A Dirq-sa11x0.c28 static void __iomem *iobase; variable
38 reg = readl_relaxed(iobase + ICMR);
40 writel_relaxed(reg, iobase + ICMR);
47 reg = readl_relaxed(iobase + ICMR);
49 writel_relaxed(reg, iobase + ICMR);
93 st->icmr = readl_relaxed(iobase + ICMR);
94 st->iclr = readl_relaxed(iobase + ICLR);
95 st->iccr = readl_relaxed(iobase + ICCR);
100 writel_relaxed(st->icmr & 0xfffff000, iobase + ICMR);
110 writel_relaxed(st->iccr, iobase
[all...]
/linux-master/drivers/rtc/
H A Drtc-asm9260.c108 void __iomem *iobase; member in struct:asm9260_rtc_priv
120 isr = ioread32(priv->iobase + HW_CIIR);
126 iowrite32(0, priv->iobase + HW_CIIR);
141 ctime0 = ioread32(priv->iobase + HW_CTIME0);
142 ctime1 = ioread32(priv->iobase + HW_CTIME1);
143 ctime2 = ioread32(priv->iobase + HW_CTIME2);
145 if (ctime1 != ioread32(priv->iobase + HW_CTIME1)) {
150 ctime0 = ioread32(priv->iobase + HW_CTIME0);
151 ctime1 = ioread32(priv->iobase + HW_CTIME1);
152 ctime2 = ioread32(priv->iobase
[all...]
/linux-master/drivers/char/tpm/
H A Dtpm_tis_synquacer.c28 void __iomem *iobase; member in struct:tpm_tis_synquacer_phy
44 *result++ = ioread8(phy->iobase + addr);
47 result[1] = ioread8(phy->iobase + addr + 1);
48 result[0] = ioread8(phy->iobase + addr);
51 result[3] = ioread8(phy->iobase + addr + 3);
52 result[2] = ioread8(phy->iobase + addr + 2);
53 result[1] = ioread8(phy->iobase + addr + 1);
54 result[0] = ioread8(phy->iobase + addr);
69 iowrite8(*value++, phy->iobase + addr);
78 iowrite8(value[3], phy->iobase
[all...]
/linux-master/drivers/bluetooth/
H A Dbluecard_cs.c162 unsigned int iobase = info->p_dev->resource[0]->start; local
171 outb(0x08 | 0x20, iobase + 0x30);
177 unsigned int iobase = info->p_dev->resource[0]->start; local
187 outb(0x18 | 0x60, iobase + 0x30);
190 outb(0x00, iobase + 0x30);
202 static int bluecard_write(unsigned int iobase, unsigned int offset, __u8 *buf, int len) argument
208 outb_p(actual, iobase + offset);
211 outb_p(buf[i], iobase + offset + i + 1);
233 unsigned int iobase = info->p_dev->resource[0]->start; local
266 outb(info->ctrl_reg, iobase
337 bluecard_read(unsigned int iobase, unsigned int offset, __u8 *buf, int size) argument
368 unsigned int iobase; local
497 unsigned int iobase; local
621 unsigned int iobase = info->p_dev->resource[0]->start; local
636 unsigned int iobase = info->p_dev->resource[0]->start; local
682 unsigned int iobase = info->p_dev->resource[0]->start; local
795 unsigned int iobase = info->p_dev->resource[0]->start; local
[all...]
H A Dbt3c_cs.c116 static inline void bt3c_address(unsigned int iobase, unsigned short addr) argument
118 outb(addr & 0xff, iobase + ADDR_L);
119 outb((addr >> 8) & 0xff, iobase + ADDR_H);
123 static inline void bt3c_put(unsigned int iobase, unsigned short value) argument
125 outb(value & 0xff, iobase + DATA_L);
126 outb((value >> 8) & 0xff, iobase + DATA_H);
130 static inline void bt3c_io_write(unsigned int iobase, unsigned short addr, unsigned short value) argument
132 bt3c_address(iobase, addr);
133 bt3c_put(iobase, value);
137 static inline unsigned short bt3c_get(unsigned int iobase) argument
147 bt3c_read(unsigned int iobase, unsigned short addr) argument
159 bt3c_write(unsigned int iobase, int fifo_size, __u8 *buf, int len) argument
189 unsigned int iobase = info->p_dev->resource[0]->start; local
218 unsigned int iobase; local
337 unsigned int iobase; local
451 unsigned int iobase, tmp, tn; local
[all...]
/linux-master/drivers/gpu/drm/i915/
H A Di915_mm.c38 resource_size_t iobase; member in struct:remap_pfn
45 if (use_dma(r->iobase))
46 return (r->sgt.dma + r->sgt.curr + r->iobase) >> PAGE_SHIFT;
65 r->sgt = __sgt_iter(__sg_next(r->sgt.sgp), use_dma(r->iobase));
125 * @iobase: Use stored dma address offset by this address or pfn if -1
131 struct scatterlist *sgl, resource_size_t iobase)
136 .sgt = __sgt_iter(sgl, use_dma(iobase)),
137 .iobase = iobase,
144 if (!use_dma(iobase))
129 remap_io_sg(struct vm_area_struct *vma, unsigned long addr, unsigned long size, struct scatterlist *sgl, resource_size_t iobase) argument
[all...]
/linux-master/drivers/mtd/maps/
H A Dl440gx.c22 static u32 iobase; variable
23 #define IOBASE iobase
91 /* Setup the pm iobase resource
98 pm_iobase->name = "pm iobase";
104 pci_read_config_dword(pm_dev, 0x40, &iobase);
105 iobase &= ~1;
106 pm_iobase->start += iobase & ~1;
107 pm_iobase->end += iobase & ~1;
115 printk(KERN_WARNING "Could not allocate pm iobase resource\n");
120 /* Set the iobase */
[all...]
/linux-master/drivers/net/hamradio/
H A Dbaycom_ser_fdx.c38 * iobase base address of the port; common values are 0x3f8, 0x2f8, 0x3e8, 0x2e8
92 #define RBR(iobase) (iobase+0)
93 #define THR(iobase) (iobase+0)
94 #define IER(iobase) (iobase+1)
95 #define IIR(iobase) (iobase+2)
96 #define FCR(iobase) (iobas
341 ser12_check_uart(unsigned int iobase) argument
570 static int iobase[NR_PORTS] = { 0x3f8, }; variable
[all...]
H A Dbaycom_ser_hdx.c30 * iobase base address of the port; common values are 0x3f8, 0x2f8, 0x3e8, 0x2e8
78 #define RBR(iobase) (iobase+0)
79 #define THR(iobase) (iobase+0)
80 #define IER(iobase) (iobase+1)
81 #define IIR(iobase) (iobase+2)
82 #define FCR(iobase) (iobas
423 ser12_check_uart(unsigned int iobase) argument
624 static int iobase[NR_PORTS] = { 0x3f8, }; variable
[all...]

Completed in 209 milliseconds

1234567891011>>