Searched refs:intc (Results 1 - 25 of 43) sorted by relevance

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/linux-master/drivers/irqchip/
H A Dirq-bcm7038-l1.c79 static inline unsigned int reg_status(struct bcm7038_l1_chip *intc, argument
82 return (0 * intc->n_words + word) * sizeof(u32);
85 static inline unsigned int reg_mask_status(struct bcm7038_l1_chip *intc, argument
88 return (1 * intc->n_words + word) * sizeof(u32);
91 static inline unsigned int reg_mask_set(struct bcm7038_l1_chip *intc, argument
94 return (2 * intc->n_words + word) * sizeof(u32);
97 static inline unsigned int reg_mask_clr(struct bcm7038_l1_chip *intc, argument
100 return (3 * intc->n_words + word) * sizeof(u32);
121 struct bcm7038_l1_chip *intc = irq_desc_get_handler_data(desc); local
127 cpu = intc
153 struct bcm7038_l1_chip *intc = irq_data_get_irq_chip_data(d); local
164 struct bcm7038_l1_chip *intc = irq_data_get_irq_chip_data(d); local
175 struct bcm7038_l1_chip *intc = irq_data_get_irq_chip_data(d); local
185 struct bcm7038_l1_chip *intc = irq_data_get_irq_chip_data(d); local
198 struct bcm7038_l1_chip *intc = irq_data_get_irq_chip_data(d); local
222 bcm7038_l1_init_one(struct device_node *dn, unsigned int idx, struct bcm7038_l1_chip *intc) argument
297 struct bcm7038_l1_chip *intc; local
323 struct bcm7038_l1_chip *intc; local
349 struct bcm7038_l1_chip *intc = irq_data_get_irq_chip_data(d); local
380 struct bcm7038_l1_chip *intc = d->host_data; local
401 struct bcm7038_l1_chip *intc; local
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H A Dirq-bcm6345-l1.c84 struct bcm6345_l1_chip *intc; member in struct:bcm6345_l1_cpu
90 static inline unsigned int reg_enable(struct bcm6345_l1_chip *intc, argument
94 return (1 * intc->n_words - word - 1) * sizeof(u32);
96 return (0 * intc->n_words + word) * sizeof(u32);
100 static inline unsigned int reg_status(struct bcm6345_l1_chip *intc, argument
104 return (2 * intc->n_words - word - 1) * sizeof(u32);
106 return (1 * intc->n_words + word) * sizeof(u32);
110 static inline unsigned int cpu_for_irq(struct bcm6345_l1_chip *intc, argument
113 return cpumask_first_and(&intc->cpumask, irq_data_get_affinity_mask(d));
119 struct bcm6345_l1_chip *intc local
144 struct bcm6345_l1_chip *intc = irq_data_get_irq_chip_data(d); local
156 struct bcm6345_l1_chip *intc = irq_data_get_irq_chip_data(d); local
168 struct bcm6345_l1_chip *intc = irq_data_get_irq_chip_data(d); local
178 struct bcm6345_l1_chip *intc = irq_data_get_irq_chip_data(d); local
190 struct bcm6345_l1_chip *intc = irq_data_get_irq_chip_data(d); local
226 bcm6345_l1_init_one(struct device_node *dn, unsigned int idx, struct bcm6345_l1_chip *intc) argument
299 struct bcm6345_l1_chip *intc; local
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H A Dirq-pruss-intc.c118 * @intc: PRUSS interrupt controller pointer
122 struct pruss_intc *intc; member in struct:pruss_host_irq_data
126 static inline u32 pruss_intc_read_reg(struct pruss_intc *intc, unsigned int reg) argument
128 return readl_relaxed(intc->base + reg);
131 static inline void pruss_intc_write_reg(struct pruss_intc *intc, argument
134 writel_relaxed(val, intc->base + reg);
137 static void pruss_intc_update_cmr(struct pruss_intc *intc, unsigned int evt, argument
145 val = pruss_intc_read_reg(intc, PRU_INTC_CMR(idx));
148 pruss_intc_write_reg(intc, PRU_INTC_CMR(idx), val);
150 dev_dbg(intc
154 pruss_intc_update_hmr(struct pruss_intc *intc, u8 ch, u8 host) argument
178 pruss_intc_map(struct pruss_intc *intc, unsigned long hwirq) argument
222 pruss_intc_unmap(struct pruss_intc *intc, unsigned long hwirq) argument
258 pruss_intc_init(struct pruss_intc *intc) argument
292 struct pruss_intc *intc = irq_data_get_irq_chip_data(data); local
300 struct pruss_intc *intc = irq_data_get_irq_chip_data(data); local
308 struct pruss_intc *intc = irq_data_get_irq_chip_data(data); local
331 struct pruss_intc *intc = irq_data_get_irq_chip_data(data); local
351 struct pruss_intc *intc = irq_data_get_irq_chip_data(data); local
375 pruss_intc_validate_mapping(struct pruss_intc *intc, int event, int channel, int host) argument
414 struct pruss_intc *intc = d->host_data; local
453 struct pruss_intc *intc = d->host_data; local
465 struct pruss_intc *intc = d->host_data; local
484 struct pruss_intc *intc = host_irq_data->intc; local
521 struct pruss_intc *intc; local
604 struct pruss_intc *intc = platform_get_drvdata(pdev); local
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H A Dirq-ingenic.c36 struct ingenic_intc_data *intc = irq_get_handler_data(irq); local
37 struct irq_domain *domain = intc->domain;
42 for (i = 0; i < intc->num_chips; i++) {
63 struct ingenic_intc_data *intc; local
70 intc = kzalloc(sizeof(*intc), GFP_KERNEL);
71 if (!intc) {
82 err = irq_set_handler_data(parent_irq, intc);
86 intc->num_chips = num_chips;
87 intc
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H A Dirq-bcm2836.c23 static struct bcm2836_arm_irqchip_intc intc __read_mostly;
29 void __iomem *reg = intc.base + reg_offset + 4 * cpu;
38 void __iomem *reg = intc.base + reg_offset + 4 * cpu;
65 writel(1 << smp_processor_id(), intc.base + LOCAL_PM_ROUTING_CLR);
70 writel(1 << smp_processor_id(), intc.base + LOCAL_PM_ROUTING_SET);
142 stat = readl_relaxed(intc.base + LOCAL_IRQ_PENDING0 + 4 * cpu);
146 generic_handle_domain_irq(intc.domain, hwirq);
161 mbox_val = readl_relaxed(intc.base + LOCAL_MAILBOX0_CLR0 + 16 * cpu);
175 intc.base + LOCAL_MAILBOX0_CLR0 + 16 * cpu);
182 void __iomem *mailbox0_base = intc
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H A Dirq-bcm2835.c87 static struct armctrl_ic intc __read_mostly;
94 writel_relaxed(HWIRQ_BIT(d->hwirq), intc.disable[HWIRQ_BANK(d->hwirq)]);
99 writel_relaxed(HWIRQ_BIT(d->hwirq), intc.enable[HWIRQ_BANK(d->hwirq)]);
145 intc.domain = irq_domain_add_linear(node, MAKE_HWIRQ(NR_BANKS, 0),
147 if (!intc.domain)
151 intc.pending[b] = base + reg_pending[b];
152 intc.enable[b] = base + reg_enable[b];
153 intc.disable[b] = base + reg_disable[b];
156 irq = irq_create_mapping(intc.domain, MAKE_HWIRQ(b, i));
163 reg = readl_relaxed(intc
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H A Dirq-vt8500.c58 /* vt8500 has 1 intc, wm8505 and wm8650 have 2 */
67 static struct vt8500_irq_data intc[VT8500_INTC_MAX]; variable in typeref:struct:vt8500_irq_data
174 base = intc[i].base;
186 generic_handle_domain_irq(intc[i].domain, irqnr);
202 intc[active_cnt].base = of_iomap(np, 0);
203 intc[active_cnt].domain = irq_domain_add_linear(node, 64,
204 &vt8500_irq_domain_ops, &intc[active_cnt]);
206 if (!intc[active_cnt].base) {
211 if (!intc[active_cnt].domain) {
218 vt8500_init_irq_hw(intc[active_cn
[all...]
H A Dirq-hip04.c228 static u16 hip04_get_cpumask(struct hip04_irq_data *intc) argument
230 void __iomem *base = intc->dist_base;
246 static void __init hip04_irq_dist_init(struct hip04_irq_data *intc) argument
250 unsigned int nr_irqs = intc->nr_irqs;
251 void __iomem *base = intc->dist_base;
258 cpumask = hip04_get_cpumask(intc);
268 static void hip04_irq_cpu_init(struct hip04_irq_data *intc) argument
270 void __iomem *dist_base = intc->dist_base;
271 void __iomem *base = intc->cpu_base;
279 cpu_mask = hip04_get_cpumask(intc);
[all...]
H A Dirq-xilinx-intc.c168 static int __init xilinx_intc_of_init(struct device_node *intc, argument
177 irqc->base = of_iomap(intc, 0);
180 ret = of_property_read_u32(intc, "xlnx,num-intr-inputs", &irqc->nr_irq);
186 ret = of_property_read_u32(intc, "xlnx,kind-of-intr", &irqc->intr_mask);
196 intc, irqc->nr_irq, irqc->intr_mask);
215 irqc->root_domain = irq_domain_add_linear(intc, irqc->nr_irq,
224 irq = irq_of_parse_and_map(intc, 0);
249 IRQCHIP_DECLARE(xilinx_intc_xps, "xlnx,xps-intc-1.00.a", xilinx_intc_of_init);
250 IRQCHIP_DECLARE(xilinx_intc_opb, "xlnx,opb-intc-1.00.c", xilinx_intc_of_init);
H A Dirq-starfive-jh8100-intc.c117 static int __init starfive_intc_init(struct device_node *intc, argument
130 irqc->base = of_iomap(intc, 0);
137 rst = of_reset_control_get_exclusive(intc, NULL);
144 clk = of_clk_get(intc, 0);
161 irqc->domain = irq_domain_add_linear(intc, STARFIVE_INTC_SRC_IRQ_NUM,
169 parent_irq = of_irq_get(intc, 0);
202 IRQCHIP_MATCH("starfive,jh8100-intc", starfive_intc_init)
H A DMakefile11 obj-$(CONFIG_DAVINCI_CP_INTC) += irq-davinci-cp-intc.o
24 obj-$(CONFIG_OMAP_IRQCHIP) += irq-omap-intc.o
49 obj-$(CONFIG_RDA_INTC) += irq-rda-intc.o
50 obj-$(CONFIG_RENESAS_INTC_IRQPIN) += irq-renesas-intc-irqpin.o
62 obj-$(CONFIG_XILINX_INTC) += irq-xilinx-intc.o
96 obj-$(CONFIG_CSKY_APB_INTC) += irq-csky-apb-intc.o
97 obj-$(CONFIG_RISCV_INTC) += irq-riscv-intc.o
99 obj-$(CONFIG_STARFIVE_JH8100_INTC) += irq-starfive-jh8100-intc.o
107 obj-$(CONFIG_TI_PRUSS_INTC) += irq-pruss-intc.o
116 obj-$(CONFIG_MST_IRQ) += irq-mst-intc
[all...]
/linux-master/arch/m68k/coldfire/
H A DMakefile19 obj-$(CONFIG_M5206) += m5206.o intc.o reset.o
20 obj-$(CONFIG_M5206e) += m5206.o intc.o reset.o
21 obj-$(CONFIG_M520x) += m520x.o intc-simr.o reset.o
22 obj-$(CONFIG_M523x) += m523x.o dma_timer.o intc-2.o reset.o
23 obj-$(CONFIG_M5249) += m5249.o intc.o intc-5249.o reset.o
24 obj-$(CONFIG_M525x) += m525x.o intc.o intc-525x.o reset.o
25 obj-$(CONFIG_M527x) += m527x.o intc-2.o reset.o
26 obj-$(CONFIG_M5272) += m5272.o intc
[all...]
/linux-master/drivers/sh/
H A DMakefile5 obj-$(CONFIG_SH_INTC) += intc/
/linux-master/arch/mips/include/asm/
H A Dtxx9pio.h21 __u32 intc; member in struct:txx9_pio_reg
/linux-master/arch/arc/kernel/
H A DMakefile10 obj-$(CONFIG_ISA_ARCOMPACT) += entry-compact.o intc-compact.o
11 obj-$(CONFIG_ISA_ARCV2) += entry-arcv2.o intc-arcv2.o
H A Dintc-compact.c54 * ARC700 core includes a simple on-chip intc supporting
59 * To reduce platform code, we assume all IRQs directly hooked-up into intc.
60 * Platforms with external intc, hence cascaded IRQs, are free to over-ride
108 init_onchip_IRQ(struct device_node *intc, struct device_node *parent) argument
113 panic("DeviceTree incore intc not a root irq controller\n");
115 root_domain = irq_domain_add_linear(intc, NR_CPU_IRQS,
129 IRQCHIP_DECLARE(arc_intc, "snps,arc700-intc", init_onchip_IRQ);
H A Dintc-arcv2.c59 * ARCv2 core intc provides multiple interrupt priorities (up to 16).
68 pr_info("archs-intc\t: %d priority levels (default %d)%s\n",
136 * core intc IRQs [16, 23]:
161 init_onchip_IRQ(struct device_node *intc, struct device_node *parent) argument
171 panic("DeviceTree incore intc not a root irq controller\n");
173 root_domain = irq_domain_add_linear(intc, nr_cpu_irqs, &arcv2_irq_ops, NULL);
191 IRQCHIP_DECLARE(arc_intc, "snps,archs-intc", init_onchip_IRQ);
H A Dmcip.c183 * Connects external "COMMON" IRQs to core intc, providing:
378 idu_of_init(struct device_node *intc, struct device_node *parent) argument
396 domain = irq_domain_add_linear(intc, nr_irqs, &idu_irq_ops, NULL);
398 /* Parent interrupts (core-intc) are already mapped */
405 * Return parent uplink IRQs (towards core intc) 24,25,.....
419 IRQCHIP_DECLARE(arcv2_idu_intc, "snps,archs-idu-intc", idu_of_init);
/linux-master/arch/sh/kernel/cpu/sh4a/
H A DMakefile12 obj-$(CONFIG_CPU_SUBTYPE_SH7786) += setup-sh7786.o intc-shx3.o
19 obj-$(CONFIG_CPU_SUBTYPE_SHX3) += setup-shx3.o intc-shx3.o
/linux-master/drivers/pci/controller/dwc/
H A Dpcie-dw-rockchip.c128 struct device_node *intc; local
130 intc = of_get_child_by_name(dev->of_node, "legacy-interrupt-controller");
131 if (!intc) {
136 rockchip->irq_domain = irq_domain_add_linear(intc, PCI_NUM_INTX,
138 of_node_put(intc);
/linux-master/drivers/pci/controller/
H A Dpci-ftpci100.c331 struct device_node *intc = of_get_next_child(p->dev->of_node, NULL); local
335 if (!intc) {
341 irq = of_irq_get(intc, 0);
344 of_node_put(intc);
348 p->irqdomain = irq_domain_add_linear(intc, PCI_NUM_INTX,
350 of_node_put(intc);
/linux-master/arch/mips/include/asm/octeon/
H A Dcvmx-sli-defs.h61 __BITFIELD_FIELD(uint64_t intc:1,
/linux-master/drivers/of/
H A Dirq.c91 "realtek,rtl-intc",
186 bool intc = of_property_read_bool(ipar, "interrupt-controller"); local
189 if (intc &&
272 if (intc) {
/linux-master/arch/arm/mach-omap2/
H A Dcommon.h35 #include <linux/irqchip/irq-omap-intc.h>
/linux-master/arch/mips/include/asm/mach-au1x00/
H A Dgpio-au1000.h25 #define MAKE_IRQ(intc, off) (AU1000_INTC##intc##_INT_BASE + (off))

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