Searched refs:h264_dec (Results 1 - 4 of 4) sorted by relevance

/linux-master/drivers/media/platform/verisilicon/
H A Dhantro_h264.c204 const struct hantro_h264_dec_ctrls *ctrls = &ctx->h264_dec.ctrls;
210 struct hantro_h264_dec_priv_tbl *tbl = ctx->h264_dec.priv.cpu;
234 const struct hantro_h264_dec_ctrls *ctrls = &ctx->h264_dec.ctrls;
237 struct hantro_h264_dec_priv_tbl *tbl = ctx->h264_dec.priv.cpu;
238 const struct v4l2_h264_dpb_entry *dpb = ctx->h264_dec.dpb;
275 ctx->h264_dec.dpb_valid = dpb_valid;
276 ctx->h264_dec.dpb_longterm = dpb_longterm;
280 tbl->poc[32] = ctx->h264_dec.cur_poc;
303 dec_param = ctx->h264_dec.ctrls.decode;
306 for (i = 0; i < ARRAY_SIZE(ctx->h264_dec
498 struct hantro_h264_dec_hw_ctx *h264_dec = &ctx->h264_dec; local
507 struct hantro_h264_dec_hw_ctx *h264_dec = &ctx->h264_dec; local
[all...]
H A Dhantro_g1_h264_dec.c24 const struct hantro_h264_dec_ctrls *ctrls = &ctx->h264_dec.ctrls;
135 vdpu_write_relaxed(vpu, ctx->h264_dec.dpb_valid, G1_REG_VALID_REF);
136 vdpu_write_relaxed(vpu, ctx->h264_dec.dpb_longterm, G1_REG_LT_REF);
150 b0_reflist = ctx->h264_dec.reflists.b0;
151 b1_reflist = ctx->h264_dec.reflists.b1;
152 p_reflist = ctx->h264_dec.reflists.p;
207 const struct hantro_h264_dec_ctrls *ctrls = &ctx->h264_dec.ctrls;
247 vdpu_write_relaxed(vpu, ctx->h264_dec.priv.dma, G1_REG_ADDR_QTABLE);
H A Drockchip_vpu2_hw_h264_dec.c195 const struct hantro_h264_dec_ctrls *ctrls = &ctx->h264_dec.ctrls;
306 b0_reflist = ctx->h264_dec.reflists.b0;
307 b1_reflist = ctx->h264_dec.reflists.b1;
308 p_reflist = ctx->h264_dec.reflists.p;
408 reg = VDPU_REG_REFER_LTERM_E(ctx->h264_dec.dpb_longterm);
411 reg = VDPU_REG_REFER_VALID_E(ctx->h264_dec.dpb_valid);
424 const struct hantro_h264_dec_ctrls *ctrls = &ctx->h264_dec.ctrls;
464 vdpu_write_relaxed(vpu, ctx->h264_dec.priv.dma, VDPU_REG_QTABLE_BASE);
H A Dhantro.h239 * @h264_dec: H.264-decoding context.
269 struct hantro_h264_dec_hw_ctx h264_dec; member in union:hantro_ctx::__anon374

Completed in 159 milliseconds