Searched refs:gate (Results 1 - 25 of 201) sorted by relevance

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/linux-master/drivers/clk/tegra/
H A Dclk-periph-gate.c18 /* Macros to assist peripheral gate clock */
19 #define read_enb(gate) \
20 readl_relaxed(gate->clk_base + (gate->regs->enb_reg))
21 #define write_enb_set(val, gate) \
22 writel_relaxed(val, gate->clk_base + (gate->regs->enb_set_reg))
23 #define write_enb_clr(val, gate) \
24 writel_relaxed(val, gate->clk_base + (gate
38 struct tegra_clk_periph_gate *gate = to_clk_periph_gate(hw); local
53 struct tegra_clk_periph_gate *gate = to_clk_periph_gate(hw); local
55 write_enb_set(periph_clk_to_bit(gate), gate); local
68 struct tegra_clk_periph_gate *gate = to_clk_periph_gate(hw); local
78 write_enb_clr(periph_clk_to_bit(gate), gate); local
83 struct tegra_clk_periph_gate *gate = to_clk_periph_gate(hw); local
98 struct tegra_clk_periph_gate *gate = to_clk_periph_gate(hw); local
113 struct tegra_clk_periph_gate *gate = to_clk_periph_gate(hw); local
140 struct tegra_clk_periph_gate *gate; local
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/linux-master/drivers/clk/mmp/
H A Dclk-gate.c3 * mmp gate clock operation source file
26 struct mmp_clk_gate *gate = to_clk_mmp_gate(hw); local
31 if (gate->lock)
32 spin_lock_irqsave(gate->lock, flags);
34 tmp = readl(gate->reg);
35 tmp &= ~gate->mask;
36 tmp |= gate->val_enable;
37 writel(tmp, gate->reg);
39 if (gate->lock)
40 spin_unlock_irqrestore(gate
53 struct mmp_clk_gate *gate = to_clk_mmp_gate(hw); local
71 struct mmp_clk_gate *gate = to_clk_mmp_gate(hw); local
97 struct mmp_clk_gate *gate; local
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/linux-master/drivers/staging/sm750fb/
H A Dddk750_power.c75 void sm750_set_current_gate(unsigned int gate) argument
78 poke32(MODE1_GATE, gate);
80 poke32(MODE0_GATE, gate);
88 u32 gate; local
90 gate = peek32(CURRENT_GATE);
92 gate |= (CURRENT_GATE_DE | CURRENT_GATE_CSC);
94 gate &= ~(CURRENT_GATE_DE | CURRENT_GATE_CSC);
96 sm750_set_current_gate(gate);
101 u32 gate; local
104 gate
118 u32 gate; local
135 u32 gate; local
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/linux-master/drivers/clk/imx/
H A Dclk-gate2.c19 * DOC: basic gateable clock which can gate and ungate its output
43 struct clk_gate2 *gate = to_clk_gate2(hw); local
46 reg = readl(gate->reg);
47 reg &= ~(gate->cgr_mask << gate->bit_idx);
49 reg |= (gate->cgr_val & gate->cgr_mask) << gate->bit_idx;
50 writel(reg, gate->reg);
55 struct clk_gate2 *gate local
72 struct clk_gate2 *gate = to_clk_gate2(hw); local
102 struct clk_gate2 *gate = to_clk_gate2(hw); local
118 struct clk_gate2 *gate = to_clk_gate2(hw); local
142 struct clk_gate2 *gate; local
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H A Dclk-gate-93.c49 struct imx93_clk_gate *gate = to_imx93_clk_gate(hw); local
52 val = readl(gate->reg + AUTHEN_OFFSET);
55 writel(val, gate->reg + LPM_CUR_OFFSET);
57 val = readl(gate->reg + DIRECT_OFFSET);
58 val &= ~(gate->mask << gate->bit_idx);
60 val |= (gate->val & gate->mask) << gate->bit_idx;
61 writel(val, gate
67 struct imx93_clk_gate *gate = to_imx93_clk_gate(hw); local
84 struct imx93_clk_gate *gate = to_imx93_clk_gate(hw); local
101 imx93_clk_gate_reg_is_enabled(struct imx93_clk_gate *gate) argument
120 struct imx93_clk_gate *gate = to_imx93_clk_gate(hw); local
135 struct imx93_clk_gate *gate = to_imx93_clk_gate(hw); local
161 struct imx93_clk_gate *gate; local
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H A Dclk-gate-exclusive.c13 * struct clk_gate_exclusive - i.MX specific gate clock which is mutually
14 * exclusive with other gate clocks
16 * @gate: the parent class
17 * @exclusive_mask: mask of gate bits which are mutually exclusive to this
18 * gate clock
20 * The imx exclusive gate clock is a subclass of basic clk_gate
21 * with an addtional mask to indicate which other gate bits in the same
22 * register is mutually exclusive to this gate clock.
25 struct clk_gate gate; member in struct:clk_gate_exclusive
31 struct clk_gate *gate local
62 struct clk_gate *gate; local
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H A Dclk-composite-7ulp.c29 struct clk_gate *gate = to_clk_gate(hw); local
38 spin_lock_irqsave(gate->lock, flags);
43 val = readl(gate->reg);
45 writel(val, gate->reg);
47 spin_unlock_irqrestore(gate->lock, flags);
76 struct clk_gate *gate = NULL; local
111 gate = kzalloc(sizeof(*gate), GFP_KERNEL);
112 if (!gate) {
117 gate_hw = &gate
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/linux-master/drivers/clk/uniphier/
H A Dclk-uniphier-gate.c25 struct uniphier_clk_gate *gate = to_uniphier_clk_gate(hw); local
27 return regmap_write_bits(gate->regmap, gate->reg, BIT(gate->bit),
28 enable ? BIT(gate->bit) : 0);
44 struct uniphier_clk_gate *gate = to_uniphier_clk_gate(hw); local
47 if (regmap_read(gate->regmap, gate->reg, &val) < 0)
50 return !!(val & BIT(gate->bit));
64 struct uniphier_clk_gate *gate; local
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/linux-master/drivers/clk/
H A Dclk-gate.c18 * DOC: basic gatable clock which can gate and ungate its output
27 static inline u32 clk_gate_readl(struct clk_gate *gate) argument
29 if (gate->flags & CLK_GATE_BIG_ENDIAN)
30 return ioread32be(gate->reg);
32 return readl(gate->reg);
35 static inline void clk_gate_writel(struct clk_gate *gate, u32 val) argument
37 if (gate->flags & CLK_GATE_BIG_ENDIAN)
38 iowrite32be(val, gate->reg);
40 writel(val, gate->reg);
58 struct clk_gate *gate local
106 struct clk_gate *gate = to_clk_gate(hw); local
135 struct clk_gate *gate; local
202 struct clk_gate *gate; local
218 struct clk_gate *gate; local
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/linux-master/drivers/clk/actions/
H A Dowl-gate.c3 // OWL gate clock driver
14 #include "owl-gate.h"
36 struct owl_gate *gate = hw_to_owl_gate(hw); local
37 struct owl_clk_common *common = &gate->common;
39 owl_gate_set(common, &gate->gate_hw, false);
44 struct owl_gate *gate = hw_to_owl_gate(hw); local
45 struct owl_clk_common *common = &gate->common;
47 owl_gate_set(common, &gate->gate_hw, true);
67 struct owl_gate *gate = hw_to_owl_gate(hw); local
68 struct owl_clk_common *common = &gate
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/linux-master/drivers/clk/sunxi/
H A Dclk-a10-mod1.c25 struct clk_gate *gate; local
39 gate = kzalloc(sizeof(*gate), GFP_KERNEL);
40 if (!gate)
46 gate->reg = reg;
47 gate->bit_idx = SUN4I_MOD1_ENABLE;
48 gate->lock = &mod1_lock;
57 &gate->hw, &clk_gate_ops, CLK_SET_RATE_PARENT);
66 kfree(gate);
H A Dclk-a10-hosc.c21 struct clk_gate *gate; local
28 /* allocate fixed-rate and gate clock structs */
32 gate = kzalloc(sizeof(struct clk_gate), GFP_KERNEL);
33 if (!gate)
38 /* set up gate and fixed rate properties */
39 gate->reg = of_iomap(node, 0);
40 gate->bit_idx = SUNXI_OSC24M_GATE;
41 gate->lock = &hosc_lock;
48 &gate->hw, &clk_gate_ops, 0);
58 kfree(gate);
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H A Dclk-a20-gmac.c45 * select the appropriate source and gate/ungate the output to the PHY.
57 struct clk_gate *gate; local
65 /* allocate mux and gate clock structs */
70 gate = kzalloc(sizeof(struct clk_gate), GFP_KERNEL);
71 if (!gate)
82 /* set up gate and fixed rate properties */
83 gate->reg = reg;
84 gate->bit_idx = SUN7I_A20_GMAC_GPIT;
85 gate->lock = &gmac_lock;
95 &gate
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H A Dclk-sun4i-pll3.c25 struct clk_gate *gate; local
40 gate = kzalloc(sizeof(*gate), GFP_KERNEL);
41 if (!gate)
44 gate->reg = reg;
45 gate->bit_idx = SUN4I_A10_PLL3_GATE_BIT;
46 gate->lock = &sun4i_a10_pll3_lock;
61 &gate->hw, &clk_gate_ops,
82 kfree(gate);
/linux-master/drivers/clk/zynqmp/
H A Dclk-gate-zynqmp.c36 struct zynqmp_clk_gate *gate = to_zynqmp_clk_gate(hw); local
38 u32 clk_id = gate->clk_id;
56 struct zynqmp_clk_gate *gate = to_zynqmp_clk_gate(hw); local
58 u32 clk_id = gate->clk_id;
76 struct zynqmp_clk_gate *gate = to_zynqmp_clk_gate(hw); local
78 u32 clk_id = gate->clk_id;
98 * zynqmp_clk_register_gate() - Register a gate clock with the clock framework
105 * Return: clock hardware of the registered clock gate
112 struct zynqmp_clk_gate *gate; local
117 /* allocate the gate */
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H A DMakefile4 obj-$(CONFIG_ARCH_ZYNQMP) += pll.o clk-gate-zynqmp.o divider.o clk-mux-zynqmp.o clkc.o
/linux-master/drivers/clk/keystone/
H A DMakefile2 obj-$(CONFIG_COMMON_CLK_KEYSTONE) += pll.o gate.o
/linux-master/drivers/clk/visconti/
H A Dclkc.c30 struct visconti_clk_gate *gate = to_visconti_clk_gate(hw); local
31 u32 clk = BIT(gate->ck_idx);
34 regmap_read(gate->regmap, gate->ckon_offset, &val);
40 struct visconti_clk_gate *gate = to_visconti_clk_gate(hw); local
41 u32 clk = BIT(gate->ck_idx);
44 spin_lock_irqsave(gate->lock, flags);
47 spin_unlock_irqrestore(gate->lock, flags);
51 regmap_update_bits(gate->regmap, gate
57 struct visconti_clk_gate *gate = to_visconti_clk_gate(hw); local
84 struct visconti_clk_gate *gate; local
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/linux-master/drivers/clk/ingenic/
H A Djz4770-cgu.c178 .gate = { CGU_REG_CLKGR1, 7 },
195 .gate = { CGU_REG_OPCR, 31, true }, // disable CCLK stop on idle
213 .gate = { CGU_REG_MSC0CDR, 31 },
220 .gate = { CGU_REG_MSC1CDR, 31 },
227 .gate = { CGU_REG_MSC2CDR, 31 },
234 .gate = { CGU_REG_CLKGR0, 26 },
241 .gate = { CGU_REG_CLKGR0, 24 },
248 .gate = { CGU_REG_CLKGR1, 9 },
255 .gate = { CGU_REG_CLKGR0, 1 },
262 .gate
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H A Djz4755-cgu.c144 .gate = { CGU_REG_CLKGR, 10 },
151 .gate = { CGU_REG_CLKGR, 9 },
171 .gate = { CGU_REG_CLKGR, 4 },
178 .gate = { CGU_REG_CLKGR, 18 },
185 .gate = { CGU_REG_CLKGR, 2 },
192 .gate = { CGU_REG_CLKGR, 8 },
200 .gate = { CGU_REG_CLKGR, 0 },
206 .gate = { CGU_REG_CLKGR, 14 },
212 .gate = { CGU_REG_CLKGR, 15 },
218 .gate
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H A Djz4760-cgu.c219 .gate = { CGU_REG_CLKGR0, 24 },
226 .gate = { CGU_REG_CLKGR1, 9 },
238 .gate = { CGU_REG_CLKGR0, 27 },
244 .gate = { CGU_REG_CLKGR0, 28 },
251 .gate = { CGU_REG_CLKGR0, 22 },
262 .gate = { CGU_REG_CLKGR1, 8 },
277 .gate = { CGU_REG_CLKGR0, 2 },
299 .gate = { CGU_REG_CLKGR0, 26 },
307 .gate = { CGU_REG_CLKGR0, 4 },
312 .gate
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H A Djz4740-cgu.c156 .gate = { CGU_REG_CLKGR, 10 },
170 .gate = { CGU_REG_CLKGR, 6 },
178 .gate = { CGU_REG_CLKGR, 4 },
185 .gate = { CGU_REG_CLKGR, 7 },
192 .gate = { CGU_REG_CLKGR, 14 },
200 .gate = { CGU_REG_SCR, 6, true },
208 .gate = { CGU_REG_CLKGR, 0 },
214 .gate = { CGU_REG_CLKGR, 15 },
220 .gate = { CGU_REG_CLKGR, 12 },
226 .gate
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H A Djz4725b-cgu.c141 .gate = { CGU_REG_CLKGR, 13 },
148 .gate = { CGU_REG_CLKGR, 9 },
163 .gate = { CGU_REG_CLKGR, 4 },
184 .gate = { CGU_REG_CLKGR, 0 },
190 .gate = { CGU_REG_CLKGR, 12 },
196 .gate = { CGU_REG_CLKGR, 7 },
202 .gate = { CGU_REG_CLKGR, 3 },
208 .gate = { CGU_REG_CLKGR, 5 },
214 .gate = { CGU_REG_CLKGR, 6 },
220 .gate
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/linux-master/drivers/clk/socfpga/
H A DMakefile2 obj-$(CONFIG_CLK_INTEL_SOCFPGA32) += clk.o clk-gate.o clk-pll.o clk-periph.o \
3 clk-pll-a10.o clk-periph-a10.o clk-gate-a10.o
5 clk-pll-s10.o clk-periph-s10.o clk-gate-s10.o \
/linux-master/drivers/clk/mediatek/
H A Dclk-gate.c15 #include "clk-gate.h"
223 const struct mtk_gate *gate = &clks[i]; local
225 if (!IS_ERR_OR_NULL(clk_data->hws[gate->id])) {
227 node, gate->id);
231 hw = mtk_clk_register_gate(dev, gate->name, gate->parent_name,
233 gate->regs->set_ofs,
234 gate->regs->clr_ofs,
235 gate->regs->sta_ofs,
236 gate
252 const struct mtk_gate *gate = &clks[i]; local
274 const struct mtk_gate *gate = &clks[i - 1]; local
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