1// SPDX-License-Identifier: GPL-2.0+
2//
3// OWL gate clock driver
4//
5// Copyright (c) 2014 Actions Semi Inc.
6// Author: David Liu <liuwei@actions-semi.com>
7//
8// Copyright (c) 2018 Linaro Ltd.
9// Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
10
11#include <linux/clk-provider.h>
12#include <linux/regmap.h>
13
14#include "owl-gate.h"
15
16void owl_gate_set(const struct owl_clk_common *common,
17		 const struct owl_gate_hw *gate_hw, bool enable)
18{
19	int set = gate_hw->gate_flags & CLK_GATE_SET_TO_DISABLE ? 1 : 0;
20	u32 reg;
21
22	set ^= enable;
23
24	regmap_read(common->regmap, gate_hw->reg, &reg);
25
26	if (set)
27		reg |= BIT(gate_hw->bit_idx);
28	else
29		reg &= ~BIT(gate_hw->bit_idx);
30
31	regmap_write(common->regmap, gate_hw->reg, reg);
32}
33
34static void owl_gate_disable(struct clk_hw *hw)
35{
36	struct owl_gate *gate = hw_to_owl_gate(hw);
37	struct owl_clk_common *common = &gate->common;
38
39	owl_gate_set(common, &gate->gate_hw, false);
40}
41
42static int owl_gate_enable(struct clk_hw *hw)
43{
44	struct owl_gate *gate = hw_to_owl_gate(hw);
45	struct owl_clk_common *common = &gate->common;
46
47	owl_gate_set(common, &gate->gate_hw, true);
48
49	return 0;
50}
51
52int owl_gate_clk_is_enabled(const struct owl_clk_common *common,
53		   const struct owl_gate_hw *gate_hw)
54{
55	u32 reg;
56
57	regmap_read(common->regmap, gate_hw->reg, &reg);
58
59	if (gate_hw->gate_flags & CLK_GATE_SET_TO_DISABLE)
60		reg ^= BIT(gate_hw->bit_idx);
61
62	return !!(reg & BIT(gate_hw->bit_idx));
63}
64
65static int owl_gate_is_enabled(struct clk_hw *hw)
66{
67	struct owl_gate *gate = hw_to_owl_gate(hw);
68	struct owl_clk_common *common = &gate->common;
69
70	return owl_gate_clk_is_enabled(common, &gate->gate_hw);
71}
72
73const struct clk_ops owl_gate_ops = {
74	.disable	= owl_gate_disable,
75	.enable		= owl_gate_enable,
76	.is_enabled	= owl_gate_is_enabled,
77};
78