Searched refs:emc_dbg (Results 1 - 4 of 4) sorted by last modified time
/linux-master/drivers/memory/tegra/ |
H A D | tegra30-emc.c | 534 u32 emc_dbg; local 555 emc_dbg = readl_relaxed(emc->regs + EMC_DBG); 689 writel_relaxed(emc_dbg | EMC_DBG_WRITE_MUX_ACTIVE, 693 writel_relaxed(emc_dbg, emc->regs + EMC_DBG); 715 writel_relaxed(emc_dbg | EMC_DBG_WRITE_MUX_ACTIVE, emc->regs + EMC_DBG); 728 writel_relaxed(emc_dbg, emc->regs + EMC_DBG); 1120 u32 fbio_cfg5, emc_cfg, emc_dbg, emc_adr_cfg; local 1155 emc_dbg = readl_relaxed(emc->regs + EMC_DBG); 1156 emc_dbg |= EMC_DBG_CFG_PRIORITY; 1157 emc_dbg [all...] |
H A D | tegra20-emc.c | 598 u32 emc_cfg, emc_dbg, emc_fbio, emc_adr_cfg; local 627 emc_dbg = readl_relaxed(emc->regs + EMC_DBG); 628 emc_dbg |= EMC_DBG_CFG_PRIORITY; 629 emc_dbg &= ~EMC_DBG_READ_MUX_ASSEMBLY; 630 emc_dbg &= ~EMC_DBG_WRITE_MUX_ACTIVE; 631 emc_dbg &= ~EMC_DBG_FORCE_UPDATE; 632 writel_relaxed(emc_dbg, emc->regs + EMC_DBG);
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H A D | tegra210-emc-core.c | 886 u32 emc_dbg = emc_readl(emc, EMC_DBG); local 889 emc_writel(emc, emc_dbg | EMC_DBG_WRITE_MUX_ACTIVE, EMC_DBG); 891 emc_writel(emc, emc_dbg & ~EMC_DBG_WRITE_MUX_ACTIVE, EMC_DBG);
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H A D | tegra210-emc-cc-r21021.c | 36 #define emc_dbg(emc, flags, ...) dev_dbg(emc->dev, __VA_ARGS__) macro 108 emc_dbg(emc, EMA_UPDATES, "%s: (s=%lu) EMA: %u\n", \ 498 emc_dbg(emc, PER_TRAIN, "Periodic training starting\n"); 559 emc_dbg(emc, EMA_WRITES, "0x%08x <= 0x%08x\n", 616 u32 emc_dbg, emc_cfg_pipe_clk, emc_pin; local 624 emc_dbg(emc, INFO, "Running clock change.\n"); 661 emc_dbg = emc_readl(emc, EMC_DBG); 675 emc_dbg(emc, INFO, "Clock change version: %d\n", 677 emc_dbg(emc, INFO, "DRAM type = %d\n", dram_type); 678 emc_dbg(em [all...] |
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