Searched refs:edp_dpcd (Results 1 - 7 of 7) sorted by relevance

/linux-master/drivers/gpu/drm/nouveau/
H A Dnouveau_backlight.c249 u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE]; local
252 ret = drm_dp_dpcd_read(&nv_conn->aux, DP_EDP_DPCD_REV, edp_dpcd,
258 if (drm_edp_backlight_supported(edp_dpcd) &&
259 (edp_dpcd[1] & DP_EDP_BACKLIGHT_AUX_ENABLE_CAP) &&
260 (edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_AUX_SET_CAP)) {
264 ret = drm_edp_backlight_init(&nv_conn->aux, &bl->edp_info, 0, edp_dpcd,
/linux-master/include/drm/display/
H A Ddrm_dp_helper.h241 * @edp_dpcd: The DPCD to check
247 * Returns: %True if @edp_dpcd indicates that VESA backlight controls are supported, %false
251 drm_edp_backlight_supported(const u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE]) argument
253 return !!(edp_dpcd[1] & DP_EDP_TCON_BACKLIGHT_ADJUSTMENT_CAP);
702 u16 driver_pwm_freq_hz, const u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE],
/linux-master/drivers/gpu/drm/display/
H A Ddrm_dp_helper.c3754 u16 driver_pwm_freq_hz, const u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE])
3838 if (edp_dpcd[2] & DP_EDP_BACKLIGHT_FREQ_AUX_SET_CAP) {
3895 * @edp_dpcd: A cached copy of the eDP DPCD
3909 u16 driver_pwm_freq_hz, const u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE],
3914 if (edp_dpcd[1] & DP_EDP_BACKLIGHT_AUX_ENABLE_CAP)
3916 if (edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_AUX_SET_CAP)
3918 if (edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_BYTE_COUNT)
3922 if (!bl->aux_set && !(edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_PWM_PIN_CAP)) {
3929 ret = drm_edp_backlight_probe_max(aux, bl, driver_pwm_freq_hz, edp_dpcd);
4012 u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZ local
3753 drm_edp_backlight_probe_max(struct drm_dp_aux *aux, struct drm_edp_backlight_info *bl, u16 driver_pwm_freq_hz, const u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE]) argument
3908 drm_edp_backlight_init(struct drm_dp_aux *aux, struct drm_edp_backlight_info *bl, u16 driver_pwm_freq_hz, const u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE], u16 *current_level, u8 *current_mode) argument
[all...]
/linux-master/drivers/gpu/drm/i915/display/
H A Dintel_dp_aux_backlight.c401 panel->vbt.backlight.pwm_freq_hz, intel_dp->edp_dpcd,
457 if (drm_edp_backlight_supported(intel_dp->edp_dpcd)) {
H A Dintel_dp.c3863 if (intel_dp->edp_dpcd[0] < DP_EDP_14)
3917 intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) ==
3918 sizeof(intel_dp->edp_dpcd)) {
3920 (int)sizeof(intel_dp->edp_dpcd),
3921 intel_dp->edp_dpcd);
3923 intel_dp->use_max_params = intel_dp->edp_dpcd[0] < DP_EDP_14;
3927 * This has to be called after intel_dp->edp_dpcd is filled, PSR checks
3928 * for SET_POWER_CAPABLE bit in intel_dp->edp_dpcd[1]
3936 if (intel_dp->edp_dpcd[
[all...]
H A Dintel_psr.c526 if (!(intel_dp->edp_dpcd[1] & DP_EDP_SET_POWER_CAP)) {
1122 if (DISPLAY_VER(dev_priv) < 14 || intel_dp->edp_dpcd[0] < DP_EDP_14b)
H A Dintel_display_types.h1772 u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE]; member in struct:intel_dp

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