Searched refs:dml_get_voltage_level (Results 1 - 6 of 6) sorted by relevance

/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn32/
H A Ddcn32_fpu.c1402 new_vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);
1457 *vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, *pipe_cnt);
1511 *vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, *pipe_cnt);
1517 // Populate dppclk to trigger a recalculate in dml_get_voltage_level
1520 *vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, *pipe_cnt);
1561 *vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, *pipe_cnt);
1991 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);
2229 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);
/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn21/
H A Ddcn21_resource.c828 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);
840 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);
/linux-master/drivers/gpu/drm/amd/display/dc/dml/
H A Ddisplay_mode_vba.h160 unsigned int dml_get_voltage_level(
319 double CachedActiveDRAMClockChangeLatencyMargin[DC__NUM_DPP__MAX]; // Cache in dml_get_voltage_level for debug purposes only
H A Ddisplay_mode_vba.c52 unsigned int dml_get_voltage_level( function
/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn30/
H A Ddcn30_resource.c1670 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);
1689 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);
/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn20/
H A Ddcn20_resource.c2051 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);

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