Searched refs:div (Results 1 - 25 of 805) sorted by relevance

1234567891011>>

/linux-master/drivers/clk/
H A Dclk-fsl-flexspi.c14 { .val = 0, .div = 1, },
15 { .val = 1, .div = 2, },
16 { .val = 2, .div = 3, },
17 { .val = 3, .div = 4, },
18 { .val = 4, .div = 5, },
19 { .val = 5, .div = 6, },
20 { .val = 6, .div = 7, },
21 { .val = 7, .div = 8, },
22 { .val = 11, .div = 12, },
23 { .val = 15, .div
[all...]
H A Dclk-divider.c51 for (clkt = table; clkt->div; clkt++)
52 if (clkt->div > maxdiv && clkt->val <= mask)
53 maxdiv = clkt->div;
62 for (clkt = table; clkt->div; clkt++)
63 if (clkt->div < mindiv)
64 mindiv = clkt->div;
85 for (clkt = table; clkt->div; clkt++)
87 return clkt->div;
106 unsigned int div)
110 for (clkt = table; clkt->div; clk
105 _get_table_val(const struct clk_div_table *table, unsigned int div) argument
116 _get_val(const struct clk_div_table *table, unsigned int div, unsigned long flags, u8 width) argument
135 unsigned int div; local
162 _is_valid_table_div(const struct clk_div_table *table, unsigned int div) argument
173 _is_valid_div(const struct clk_div_table *table, unsigned int div, unsigned long flags) argument
183 _round_up_table(const struct clk_div_table *table, int div) argument
201 _round_down_table(const struct clk_div_table *table, int div) argument
223 int div = DIV_ROUND_UP_ULL((u64)parent_rate, rate); local
276 _next_div(const struct clk_div_table *table, int div, unsigned long flags) argument
350 int div; local
365 int div; local
474 unsigned int div, value; local
544 struct clk_divider *div; local
629 struct clk_divider *div; local
649 struct clk_divider *div; local
[all...]
H A Dclk-milbeaut.c83 u8 div; member in struct:m10v_clk_div_fixed_data
101 { .val = 0, .div = 8 },
102 { .val = 1, .div = 9 },
103 { .val = 2, .div = 10 },
104 { .val = 3, .div = 15 },
105 { .div = 0 },
109 { .val = 1, .div = 2 },
110 { .val = 3, .div = 4 },
111 { .div = 0 },
115 { .val = 3, .div
463 struct m10v_clk_divider *div; local
[all...]
/linux-master/drivers/clk/berlin/
H A Dberlin2-div.c16 #include "berlin2-div.h"
36 * (D) constant div-by-3 clock divider
38 * (F) constant div-by-3 clock mux controlled by <D3Switch>
46 * Also, clock gate and pll mux is not available on every div cell, so
67 struct berlin2_div *div = to_berlin2_div(hw); local
68 struct berlin2_div_map *map = &div->map;
71 if (div->lock)
72 spin_lock(div->lock);
74 reg = readl_relaxed(div->base + map->gate_offs);
77 if (div
85 struct berlin2_div *div = to_berlin2_div(hw); local
104 struct berlin2_div *div = to_berlin2_div(hw); local
121 struct berlin2_div *div = to_berlin2_div(hw); local
152 struct berlin2_div *div = to_berlin2_div(hw); local
179 struct berlin2_div *div = to_berlin2_div(hw); local
237 struct berlin2_div *div; local
[all...]
/linux-master/drivers/clk/mxs/
H A Dclk-div.c38 struct clk_div *div = to_clk_div(hw); local
40 return div->ops->recalc_rate(&div->divider.hw, parent_rate);
46 struct clk_div *div = to_clk_div(hw); local
48 return div->ops->round_rate(&div->divider.hw, rate, prate);
54 struct clk_div *div = to_clk_div(hw); local
57 ret = div->ops->set_rate(&div->divider.hw, rate, parent_rate);
59 ret = mxs_clk_wait(div
73 struct clk_div *div; local
[all...]
/linux-master/drivers/clk/baikal-t1/
H A Dccu-div.c12 #define pr_fmt(fmt) "bt1-ccu-div: " fmt
27 #include "ccu-div.h"
61 unsigned long div)
63 u64 ns = 4ULL * (div ?: 1) * NSEC_PER_SEC;
71 unsigned long div)
73 return ref_clk / (div ?: 1);
76 static int ccu_div_var_update_clkdiv(struct ccu_div *div, argument
87 if (div->features & CCU_DIV_LOCK_SHIFTED)
92 regmap_update_bits(div->sys_regs, div
60 ccu_div_lock_delay_ns(unsigned long ref_clk, unsigned long div) argument
70 ccu_div_calc_freq(unsigned long ref_clk, unsigned long div) argument
113 struct ccu_div *div = to_ccu_div(hw); local
142 struct ccu_div *div = to_ccu_div(hw); local
155 struct ccu_div *div = to_ccu_div(hw); local
165 struct ccu_div *div = to_ccu_div(hw); local
175 struct ccu_div *div = to_ccu_div(hw); local
188 struct ccu_div *div = to_ccu_div(hw); local
199 struct ccu_div *div = to_ccu_div(hw); local
210 struct ccu_div *div = to_ccu_div(hw); local
234 struct ccu_div *div = to_ccu_div(hw); local
250 struct ccu_div *div = to_ccu_div(hw); local
284 struct ccu_div *div = to_ccu_div(hw); local
306 struct ccu_div *div = to_ccu_div(hw); local
314 struct ccu_div *div = to_ccu_div(hw); local
328 struct ccu_div *div; member in struct:ccu_div_dbgfs_bit
359 struct ccu_div *div = bit->div; local
372 struct ccu_div *div = priv; local
400 struct ccu_div *div = bit->div; local
413 struct ccu_div *div = priv; local
426 struct ccu_div *div = priv; local
437 struct ccu_div *div = to_ccu_div(hw); local
484 struct ccu_div *div = to_ccu_div(hw); local
502 struct ccu_div *div = to_ccu_div(hw); local
517 struct ccu_div *div = to_ccu_div(hw); local
577 struct ccu_div *div; local
643 ccu_div_hw_unregister(struct ccu_div *div) argument
[all...]
H A DMakefile3 obj-$(CONFIG_CLK_BT1_CCU_DIV) += ccu-div.o clk-ccu-div.o
/linux-master/drivers/clk/sprd/
H A Ddiv.c10 #include "div.h"
18 cd->div.width, 0);
22 const struct sprd_div_internal *div,
28 regmap_read(common->regmap, common->reg + div->offset, &reg);
29 val = reg >> div->shift;
30 val &= (1 << div->width) - 1;
33 div->width);
42 return sprd_div_helper_recalc_rate(&cd->common, &cd->div, parent_rate);
46 const struct sprd_div_internal *div,
54 div
21 sprd_div_helper_recalc_rate(struct sprd_clk_common *common, const struct sprd_div_internal *div, unsigned long parent_rate) argument
45 sprd_div_helper_set_rate(const struct sprd_clk_common *common, const struct sprd_div_internal *div, unsigned long rate, unsigned long parent_rate) argument
[all...]
/linux-master/drivers/clk/imx/
H A Dclk-divider-gate.c21 struct clk_divider *div = to_clk_divider(hw); local
23 return container_of(div, struct clk_divider_gate, divider);
29 struct clk_divider *div = to_clk_divider(hw); local
32 val = readl(div->reg) >> div->shift;
33 val &= clk_div_mask(div->width);
37 return divider_recalc_rate(hw, parent_rate, val, div->table,
38 div->flags, div->width);
45 struct clk_divider *div local
77 struct clk_divider *div = to_clk_divider(hw); local
106 struct clk_divider *div = to_clk_divider(hw); local
129 struct clk_divider *div = to_clk_divider(hw); local
146 struct clk_divider *div = to_clk_divider(hw); local
[all...]
/linux-master/drivers/clk/ti/
H A Ddivider.c26 for (clkt = table; clkt->div; clkt++)
28 return clkt->div;
41 for (clkt = divider->table; clkt->div; clkt++)
72 unsigned int div)
76 for (clkt = table; clkt->div; clkt++)
77 if (clkt->div == div)
82 static unsigned int _get_val(struct clk_omap_divider *divider, u8 div) argument
85 return div;
87 return __ffs(div);
71 _get_table_val(const struct clk_div_table *table, unsigned int div) argument
97 unsigned int div, val; local
119 _is_valid_table_div(const struct clk_div_table *table, unsigned int div) argument
130 _is_valid_div(struct clk_omap_divider *divider, unsigned int div) argument
144 int div = DIV_ROUND_UP_ULL((u64)parent_rate, rate); local
229 int div; local
239 unsigned int div, value; local
308 _register_divider(struct device_node *node, u32 flags, struct clk_omap_divider *div) argument
383 ti_clk_get_div_table(struct device_node *node, struct clk_omap_divider *div) argument
469 ti_clk_divider_populate(struct device_node *node, struct clk_omap_divider *div, u32 *flags) argument
516 struct clk_omap_divider *div; local
540 struct clk_omap_divider *div; local
[all...]
/linux-master/drivers/clk/sunxi/
H A Dclk-sun6i-ar100.c27 unsigned long div; local
34 div = DIV_ROUND_UP(req->parent_rate, req->rate);
36 if (div < 32)
38 else if (div >> 1 < 32)
40 else if (div >> 2 < 32)
45 div >>= shift;
47 if (div > 32)
48 div = 32;
50 req->rate = (req->parent_rate >> shift) / div;
51 req->m = div
[all...]
/linux-master/include/linux/platform_data/
H A Dhwmon-s3c.h17 * @div: Divide the value from the ADC by this.
20 * hwmon expects (mV) by result = (value_read * @mult) / @div.
25 unsigned int div; member in struct:s3c_hwmon_chcfg
/linux-master/drivers/clk/meson/
H A Dclk-cpu-dyndiv.h14 struct parm div; member in struct:meson_clk_cpu_dyndiv_data
H A Dclk-cpu-dyndiv.c26 meson_parm_read(clk->map, &data->div),
27 NULL, 0, data->div.width);
36 return divider_determine_rate(hw, req, NULL, data->div.width, 0);
47 ret = divider_get_val(rate, parent_rate, NULL, data->div.width, 0);
51 val = (unsigned int)ret << data->div.shift;
57 return regmap_update_bits(clk->map, data->div.reg_off,
58 SETPMASK(data->div.width, data->div.shift) |
H A Dclk-regmap.c63 struct clk_regmap_div_data *div = clk_get_regmap_div_data(clk); local
67 ret = regmap_read(clk->map, div->offset, &val);
72 val >>= div->shift;
73 val &= clk_div_mask(div->width);
74 return divider_recalc_rate(hw, prate, val, div->table, div->flags,
75 div->width);
82 struct clk_regmap_div_data *div = clk_get_regmap_div_data(clk); local
87 if (div->flags & CLK_DIVIDER_READ_ONLY) {
88 ret = regmap_read(clk->map, div
107 struct clk_regmap_div_data *div = clk_get_regmap_div_data(clk); local
[all...]
H A Dsclk-div.h14 struct parm div; member in struct:meson_sclk_div_data
/linux-master/drivers/clk/bcm/
H A Dclk-iproc-asiu.c22 struct iproc_asiu_div div; member in struct:iproc_asiu_clk
82 val = readl(asiu->div_base + clk->div.offset);
83 if ((val & (1 << clk->div.en_shift)) == 0) {
89 div_h = (val >> clk->div.high_shift) & bit_mask(clk->div.high_width);
91 div_l = (val >> clk->div.low_shift) & bit_mask(clk->div.low_width);
104 unsigned int div; local
112 div = DIV_ROUND_CLOSEST(*parent_rate, rate);
113 if (div <
124 unsigned int div, div_h, div_l; local
175 iproc_asiu_setup(struct device_node *node, const struct iproc_asiu_div *div, const struct iproc_asiu_gate *gate, unsigned int num_clks) argument
[all...]
/linux-master/drivers/clk/tegra/
H A Dclk-divider.c24 int div; local
26 div = div_frac_get(rate, parent_rate, divider->width,
29 if (div < 0)
32 return div;
40 int div, mul; local
49 div = (reg >> divider->shift) & div_mask(divider);
52 div += mul;
55 rate += div - 1;
56 do_div(rate, div);
65 int div, mu local
84 int div; local
[all...]
/linux-master/drivers/mmc/host/
H A Dmeson-mx-sdhc-clkc.c17 struct clk_divider div; member in struct:meson_mx_sdhc_clkc
32 { .div = 6, .val = 5, },
33 { .div = 8, .val = 7, },
34 { .div = 9, .val = 8, },
35 { .div = 10, .val = 9, },
36 { .div = 12, .val = 11, },
37 { .div = 16, .val = 15, },
38 { .div = 18, .val = 17, },
39 { .div = 34, .val = 33, },
40 { .div
[all...]
/linux-master/sound/soc/codecs/
H A Dadau-utils.c19 unsigned int div; local
25 div = 0;
28 div = DIV_ROUND_UP(freq_in, 13500000);
29 freq_in /= div;
35 div--;
40 div = 0;
42 if (n > 0xffff || m > 0xffff || div > 3 || r > 8 || r < 2)
50 regs[4] = (r << 3) | (div << 1);
/linux-master/sound/aoa/soundbus/i2sbus/
H A Dinterface.h89 # define I2S_SF_MCLKDIV_OTHER(div) (((div/2-1)<<I2S_SF_MCLKDIV_SHIFT)&I2S_SF_MCLKDIV_MASK)
90 static inline int i2s_sf_mclkdiv(int div, int *out) argument
94 switch(div) {
100 if (div%2) return -1;
101 d = div/2-1;
104 *out |= I2S_SF_MCLKDIV_OTHER(div);
116 # define I2S_SF_SCLKDIV_OTHER(div) (((div/2-1)<<I2S_SF_SCLKDIV_SHIFT)&I2S_SF_SCLKDIV_MASK)
117 static inline int i2s_sf_sclkdiv(int div, in argument
[all...]
/linux-master/drivers/media/i2c/
H A Daptina-pll.c24 unsigned int div; local
41 div = gcd(pll->pix_clock, pll->ext_clock);
42 pll->m = pll->pix_clock / div;
43 div = pll->ext_clock / div;
58 mf_min = max(mf_min, limits->n_min * limits->p1_min / div);
62 mf_max = min(mf_max, DIV_ROUND_UP(limits->n_max * limits->p1_max, div));
77 * 3. div * mf is a multiple of p1, in order to compute
78 * n = div * mf / p1
94 * mf_inc = p1 / gcd(div, p
[all...]
/linux-master/drivers/clk/actions/
H A Dowl-divider.c29 struct owl_divider *div = hw_to_owl_divider(hw); local
31 return owl_divider_helper_round_rate(&div->common, &div->div_hw,
55 struct owl_divider *div = hw_to_owl_divider(hw); local
57 return owl_divider_helper_recalc_rate(&div->common,
58 &div->div_hw, parent_rate);
84 struct owl_divider *div = hw_to_owl_divider(hw); local
86 return owl_divider_helper_set_rate(&div->common, &div->div_hw,
/linux-master/drivers/gpu/drm/mcde/
H A Dmcde_clk_div.c47 int best_div = 1, div; local
53 for (div = 1; div < max_div; div++) {
57 this_prate = clk_hw_round_rate(parent, rate * div);
60 div_rate = DIV_ROUND_UP_ULL(this_prate, div);
64 best_div = div;
77 int div = mcde_clk_div_choose_div(hw, rate, prate, true); local
79 return DIV_ROUND_UP_ULL(*prate, div);
88 int div; local
113 int div = mcde_clk_div_choose_div(hw, rate, &prate, false); local
[all...]
/linux-master/drivers/clk/hisilicon/
H A Dclkdivider-hi6220.c29 * @table: the div table that the divider supports
104 struct hi6220_clk_divider *div; local
112 div = kzalloc(sizeof(*div), GFP_KERNEL);
113 if (!div)
122 kfree(div);
127 table[i].div = min_div + i;
128 table[i].val = table[i].div - 1;
138 div->reg = reg;
139 div
[all...]

Completed in 335 milliseconds

1234567891011>>