Searched refs:dcss_writel (Results 1 - 7 of 7) sorted by relevance

/linux-master/drivers/gpu/drm/imx/dcss/
H A Ddcss-blkctl.c32 dcss_writel(0, blkctl->base_reg + DCSS_BLKCTL_CONTROL0);
34 dcss_writel(DISPMIX_PIXCLK_SEL,
H A Ddcss-ss.c76 dcss_writel(val, ss->base_reg + ofs);
109 dcss_writel(0, ss->base_reg + DCSS_SS_SYS_CTRL);
172 dcss_writel(0, ss->base_reg + DCSS_SS_SYS_CTRL);
H A Ddcss-ctxld.c144 dcss_writel(RD_ERR_EN | SB_HP_COMP_EN |
279 dcss_writel(db_base, ctxld->ctxld_reg + DCSS_CTXLD_DB_BASE_ADDR);
280 dcss_writel(db_cnt, ctxld->ctxld_reg + DCSS_CTXLD_DB_COUNT);
290 dcss_writel(sb_base, ctxld->ctxld_reg + DCSS_CTXLD_SB_BASE_ADDR);
291 dcss_writel(sb_count, ctxld->ctxld_reg + DCSS_CTXLD_SB_COUNT);
H A Ddcss-dtg.c101 dcss_writel(val, dtg->base_reg + ofs);
119 dcss_writel(status & LINE0_IRQ, dtg->base_reg + DCSS_DTG_INT_CONTROL);
313 dcss_writel(dtg->control_status,
348 dcss_writel(status & LINE1_IRQ,
364 dcss_writel(status & LINE0_IRQ,
H A Ddcss-dpr.c148 dcss_writel(0xff, ch->base_reg + DCSS_DPR_IRQ_MASK);
181 dcss_writel(0, ch->base_reg + DCSS_DPR_SYSTEM_CTRL0);
H A Ddcss-dev.h19 #define dcss_writel(v, c) writel((v), (c)) macro
H A Ddcss-scaler.c343 dcss_writel(0, ch->base_reg + DCSS_SCALER_CTRL);

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