Searched refs:ctrl_reg (Results 1 - 25 of 79) sorted by relevance

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/linux-master/drivers/misc/ibmasm/
H A Dlowlevel.h53 void __iomem *ctrl_reg = base_address + INTR_CONTROL_REGISTER; local
54 writel( readl(ctrl_reg) & ~mask, ctrl_reg);
59 void __iomem *ctrl_reg = base_address + INTR_CONTROL_REGISTER; local
60 writel( readl(ctrl_reg) | mask, ctrl_reg);
/linux-master/drivers/watchdog/
H A Dmachzwd.c188 unsigned int ctrl_reg = 0; local
196 ctrl_reg = zf_get_control();
197 ctrl_reg |= (ENABLE_WD1|ENABLE_WD2); /* disable wd1 and wd2 */
198 ctrl_reg &= ~(ENABLE_WD1|ENABLE_WD2);
199 zf_set_control(ctrl_reg);
211 unsigned int ctrl_reg = 0; local
227 ctrl_reg = zf_get_control();
228 ctrl_reg |= (ENABLE_WD1|zf_action);
229 zf_set_control(ctrl_reg);
238 unsigned int ctrl_reg local
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H A Dmeson_gxbb_wdt.c166 u32 ctrl_reg; local
194 ctrl_reg = readl(data->reg_base + GXBB_WDT_CTRL_REG) &
197 if (ctrl_reg) {
207 ctrl_reg |= ((clk_get_rate(data->clk) / 1000) &
213 writel(ctrl_reg, data->reg_base + GXBB_WDT_CTRL_REG);
/linux-master/drivers/clk/microchip/
H A Dclk-core.h21 const u32 ctrl_reg; member in struct:pic32_sys_pll_data
38 const u32 ctrl_reg; member in struct:pic32_ref_osc_data
45 const u32 ctrl_reg; member in struct:pic32_periph_clk_data
H A Dclk-core.c91 void __iomem *ctrl_reg; member in struct:pic32_periph_clk
101 return readl(pb->ctrl_reg) & PB_DIV_ENABLE;
108 writel(PB_DIV_ENABLE, PIC32_SET(pb->ctrl_reg));
116 writel(PB_DIV_ENABLE, PIC32_CLR(pb->ctrl_reg));
147 return ((readl(pb->ctrl_reg) >> PB_DIV_SHIFT) & PB_DIV_MASK) + 1;
174 err = readl_poll_timeout(pb->ctrl_reg, v, v & PB_DIV_READY,
185 v = readl(pb->ctrl_reg);
191 writel(v, pb->ctrl_reg);
196 err = readl_poll_timeout(pb->ctrl_reg, v, v & PB_DIV_READY,
226 pbclk->ctrl_reg
240 void __iomem *ctrl_reg; member in struct:pic32_ref_osc
582 void __iomem *ctrl_reg; member in struct:pic32_sys_pll
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/linux-master/drivers/phy/marvell/
H A Dphy-berlin-sata.c66 static inline void phy_berlin_sata_reg_setbits(void __iomem *ctrl_reg, argument
72 writel(phy_base + reg, ctrl_reg + PORT_VSR_ADDR);
75 regval = readl(ctrl_reg + PORT_VSR_DATA);
78 writel(regval, ctrl_reg + PORT_VSR_DATA);
85 void __iomem *ctrl_reg = priv->base + 0x60 + (desc->index * 0x80); local
105 phy_berlin_sata_reg_setbits(ctrl_reg, priv->phy_base, 0x01,
110 phy_berlin_sata_reg_setbits(ctrl_reg, priv->phy_base, 0x25,
114 phy_berlin_sata_reg_setbits(ctrl_reg, priv->phy_base, 0x23,
118 phy_berlin_sata_reg_setbits(ctrl_reg, priv->phy_base, 0x02,
122 regval = readl(ctrl_reg
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/linux-master/drivers/pci/hotplug/
H A Dshpchp.h177 struct ctrl_reg { struct
195 BASE_OFFSET = offsetof(struct ctrl_reg, base_offset),
196 SLOT_AVAIL1 = offsetof(struct ctrl_reg, slot_avail1),
197 SLOT_AVAIL2 = offsetof(struct ctrl_reg, slot_avail2),
198 SLOT_CONFIG = offsetof(struct ctrl_reg, slot_config),
199 SEC_BUS_CONFIG = offsetof(struct ctrl_reg, sec_bus_config),
200 MSI_CTRL = offsetof(struct ctrl_reg, msi_ctrl),
201 PROG_INTERFACE = offsetof(struct ctrl_reg, prog_interface),
202 CMD = offsetof(struct ctrl_reg, cmd),
203 CMD_STATUS = offsetof(struct ctrl_reg, cmd_statu
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H A Dcpqphp.h108 struct ctrl_reg { /* offset */ struct
140 SLOT_RST = offsetof(struct ctrl_reg, slot_RST),
141 SLOT_ENABLE = offsetof(struct ctrl_reg, slot_enable),
142 MISC = offsetof(struct ctrl_reg, misc),
143 LED_CONTROL = offsetof(struct ctrl_reg, led_control),
144 INT_INPUT_CLEAR = offsetof(struct ctrl_reg, int_input_clear),
145 INT_MASK = offsetof(struct ctrl_reg, int_mask),
146 CTRL_RESERVED0 = offsetof(struct ctrl_reg, reserved0),
147 CTRL_RESERVED1 = offsetof(struct ctrl_reg, reserved1),
148 CTRL_RESERVED2 = offsetof(struct ctrl_reg, reserved
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/linux-master/drivers/bluetooth/
H A Dbluecard_cs.c79 unsigned char ctrl_reg; member in struct:bluecard_info
265 info->ctrl_reg |= REG_CONTROL_RTS;
266 outb(info->ctrl_reg, iobase + REG_CONTROL);
307 info->ctrl_reg &= ~0x03;
308 info->ctrl_reg |= baud_reg;
309 outb(info->ctrl_reg, iobase + REG_CONTROL);
312 info->ctrl_reg &= ~REG_CONTROL_RTS;
313 outb(info->ctrl_reg, iobase + REG_CONTROL);
512 info->ctrl_reg &= ~REG_CONTROL_INTERRUPT;
513 outb(info->ctrl_reg, iobas
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/linux-master/drivers/ntb/hw/epf/
H A Dntb_hw_epf.c75 void __iomem *ctrl_reg; member in struct:ntb_epf_dev
108 writel(argument, ndev->ctrl_reg + NTB_EPF_ARGUMENT);
109 writel(command, ndev->ctrl_reg + NTB_EPF_COMMAND);
114 status = readw(ndev->ctrl_reg + NTB_EPF_CMD_STATUS);
132 writew(0, ndev->ctrl_reg + NTB_EPF_CMD_STATUS);
200 status = readw(ndev->ctrl_reg + NTB_EPF_LINK_STATUS);
216 offset = readl(ndev->ctrl_reg + NTB_EPF_SPAD_OFFSET);
219 return readl(ndev->ctrl_reg + offset);
234 offset = readl(ndev->ctrl_reg + NTB_EPF_SPAD_OFFSET);
236 writel(val, ndev->ctrl_reg
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/linux-master/drivers/net/wireless/st/cw1200/
H A Dbh.c173 u16 *ctrl_reg)
178 ST90TDS_CONTROL_REG_ID, ctrl_reg);
181 ST90TDS_CONTROL_REG_ID, ctrl_reg);
191 u16 ctrl_reg; local
208 ret = cw1200_bh_read_ctrl_reg(priv, &ctrl_reg);
215 if (ctrl_reg & ST90TDS_CONT_RDY_BIT) {
233 uint16_t *ctrl_reg,
247 read_len = (*ctrl_reg & ST90TDS_CONT_NEXT_LEN_MASK) * 2;
254 read_len, *ctrl_reg);
288 *ctrl_reg
172 cw1200_bh_read_ctrl_reg(struct cw1200_common *priv, u16 *ctrl_reg) argument
232 cw1200_bh_rx_helper(struct cw1200_common *priv, uint16_t *ctrl_reg, int *tx) argument
413 u16 ctrl_reg = 0; local
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/linux-master/drivers/clk/hisilicon/
H A Dclk-hix5hd2.c136 u32 ctrl_reg; member in struct:hix5hd2_complex_clock
148 void __iomem *ctrl_reg; member in struct:hix5hd2_clk_complex
174 val = readl_relaxed(clk->ctrl_reg);
176 writel_relaxed(val, clk->ctrl_reg);
178 writel_relaxed(val, clk->ctrl_reg);
203 val = readl_relaxed(clk->ctrl_reg);
205 writel_relaxed(val, clk->ctrl_reg);
218 val = readl_relaxed(clk->ctrl_reg);
221 writel_relaxed(val, clk->ctrl_reg);
236 val = readl_relaxed(clk->ctrl_reg);
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/linux-master/drivers/spi/
H A Dspi-cadence.c155 u32 ctrl_reg = 0; local
158 ctrl_reg |= CDNS_SPI_CR_DEFAULT;
161 ctrl_reg |= CDNS_SPI_CR_PERI_SEL;
171 cdns_spi_write(xspi, CDNS_SPI_CR, ctrl_reg);
183 u32 ctrl_reg; local
185 ctrl_reg = cdns_spi_read(xspi, CDNS_SPI_CR);
189 ctrl_reg |= CDNS_SPI_CR_SSCTRL;
192 ctrl_reg &= ~CDNS_SPI_CR_SSCTRL;
194 ctrl_reg |= ((~(CDNS_SPI_SS0 << spi_get_chipselect(spi, 0))) <<
198 ctrl_reg |
214 u32 ctrl_reg, new_ctrl_reg; local
257 u32 ctrl_reg, baud_rate_val; local
491 u32 ctrl_reg; local
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H A Dspi-jcore.c44 static int jcore_spi_wait(void __iomem *ctrl_reg) argument
49 if (!(readl(ctrl_reg) & JCORE_SPI_STAT_BUSY))
59 void __iomem *ctrl_reg = hw->base + CTRL_REG; local
61 if (jcore_spi_wait(ctrl_reg))
65 writel(hw->cs_reg | hw->speed_reg, ctrl_reg);
102 void __iomem *ctrl_reg = hw->base + CTRL_REG; local
120 if (jcore_spi_wait(ctrl_reg))
124 writel(xmit, ctrl_reg);
126 if (jcore_spi_wait(ctrl_reg))
/linux-master/drivers/net/wireless/silabs/wfx/
H A Dbh.c137 int ctrl_reg, piggyback; local
142 ctrl_reg = piggyback;
144 ctrl_reg = atomic_xchg(&wdev->hif.ctrl_reg, 0);
146 ctrl_reg = 0;
147 if (!(ctrl_reg & CTRL_NEXT_LEN_MASK))
149 /* ctrl_reg units are 16bits words */
150 len = (ctrl_reg & CTRL_NEXT_LEN_MASK) * 2;
159 ctrl_reg = atomic_xchg(&wdev->hif.ctrl_reg, piggybac
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H A Dbh.h22 atomic_t ctrl_reg; member in struct:wfx_hif
/linux-master/drivers/clocksource/
H A Dtimer-cadence-ttc.c113 u32 ctrl_reg; local
116 ctrl_reg = readl_relaxed(timer->base_addr + TTC_CNT_CNTRL_OFFSET);
117 ctrl_reg |= TTC_CNT_CNTRL_DISABLE_MASK;
118 writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);
126 ctrl_reg |= CNT_CNTRL_RESET;
127 ctrl_reg &= ~TTC_CNT_CNTRL_DISABLE_MASK;
128 writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);
201 u32 ctrl_reg; local
203 ctrl_reg = readl_relaxed(timer->base_addr + TTC_CNT_CNTRL_OFFSET);
204 ctrl_reg |
229 u32 ctrl_reg; local
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/linux-master/drivers/input/rmi4/
H A Drmi_f30.c275 u8 *ctrl_reg = f30->ctrl_regs; local
300 f30->register_count, &ctrl_reg);
303 sizeof(u8), &ctrl_reg);
307 f30->register_count, &ctrl_reg);
310 f30->register_count, &ctrl_reg);
315 f30->register_count, &ctrl_reg);
319 &ctrl_reg);
325 f30->gpioled_count, &ctrl_reg);
331 f30->gpioled_count, &ctrl_reg);
336 f30->register_count, &ctrl_reg);
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/linux-master/drivers/regulator/
H A Dvctrl-regulator.c323 struct regulator *ctrl_reg)
332 n_voltages = regulator_count_voltages(ctrl_reg);
338 ctrl_uV = regulator_list_voltage(ctrl_reg, i);
358 ctrl_uV = regulator_list_voltage(ctrl_reg, i);
450 struct regulator *ctrl_reg; local
465 ctrl_reg = devm_regulator_get(&pdev->dev, "ctrl");
466 if (IS_ERR(ctrl_reg))
467 return PTR_ERR(ctrl_reg);
477 if ((regulator_get_linear_step(ctrl_reg) == 1) ||
478 (regulator_count_voltages(ctrl_reg)
322 vctrl_init_vtable(struct platform_device *pdev, struct regulator *ctrl_reg) argument
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/linux-master/drivers/fpga/
H A Dsocfpga.c337 u32 ctrl_reg; local
346 ctrl_reg = socfpga_fpga_readl(priv, SOCFPGA_FPGMGR_CTL_OFST);
347 ctrl_reg &= ~SOCFPGA_FPGMGR_CTL_CDRATIO_MASK;
348 ctrl_reg &= ~SOCFPGA_FPGMGR_CTL_CFGWDTH_MASK;
349 ctrl_reg |= cfgmgr_modes[mode].ctrl;
352 ctrl_reg &= ~SOCFPGA_FPGMGR_CTL_NCE;
353 socfpga_fpga_writel(priv, SOCFPGA_FPGMGR_CTL_OFST, ctrl_reg);
361 u32 ctrl_reg, status; local
378 ctrl_reg = socfpga_fpga_readl(priv, SOCFPGA_FPGMGR_CTL_OFST);
379 ctrl_reg |
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/linux-master/drivers/i2c/busses/
H A Di2c-cadence.c184 * @ctrl_reg: Cached value of the control register.
212 u32 ctrl_reg; member in struct:cdns_i2c
570 unsigned int ctrl_reg; local
582 ctrl_reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET);
583 ctrl_reg |= CDNS_I2C_CR_RW | CDNS_I2C_CR_CLR_FIFO;
600 ctrl_reg |= CDNS_I2C_CR_HOLD;
602 cdns_i2c_writereg(ctrl_reg, CDNS_I2C_CR_OFFSET);
624 if (ctrl_reg & CDNS_I2C_CR_HOLD) {
635 ctrl_reg &= ~CDNS_I2C_CR_HOLD;
647 cdns_i2c_writereg(ctrl_reg, CDNS_I2C_CR_OFFSE
668 unsigned int ctrl_reg; local
1079 unsigned int ctrl_reg; local
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/linux-master/drivers/net/wireless/realtek/rtw88/
H A Dsec.c127 u16 ctrl_reg; local
133 ctrl_reg = rtw_read16(rtwdev, REG_CR);
134 ctrl_reg |= RTW_SEC_ENGINE_EN;
135 rtw_write16(rtwdev, REG_CR, ctrl_reg);
/linux-master/drivers/tty/serial/
H A Dxilinx_uartps.c605 u32 ctrl_reg; local
635 ctrl_reg = readl(port->membase + CDNS_UART_CR);
636 ctrl_reg |= CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS;
637 writel(ctrl_reg, port->membase + CDNS_UART_CR);
662 ctrl_reg = readl(port->membase + CDNS_UART_CR);
663 ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST;
664 writel(ctrl_reg, port->membase + CDNS_UART_CR);
676 ctrl_reg = readl(port->membase + CDNS_UART_CR);
677 ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS);
678 ctrl_reg |
819 unsigned int ctrl_reg, mode_reg; local
1278 unsigned int ctrl_reg; local
1502 u32 ctrl_reg; local
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/linux-master/drivers/rtc/
H A Drtc-rk808.c45 unsigned int ctrl_reg; member in struct:rk_rtc_compat_reg
103 ret = regmap_update_bits(rk808_rtc->regmap, rk808_rtc->creg->ctrl_reg,
117 ret = regmap_update_bits(rk808_rtc->regmap, rk808_rtc->creg->ctrl_reg,
163 ret = regmap_update_bits(rk808_rtc->regmap, rk808_rtc->creg->ctrl_reg,
178 ret = regmap_update_bits(rk808_rtc->regmap, rk808_rtc->creg->ctrl_reg,
363 .ctrl_reg = RK808_RTC_CTRL_REG,
371 .ctrl_reg = RK817_RTC_CTRL_REG,
403 ret = regmap_update_bits(rk808_rtc->regmap, rk808_rtc->creg->ctrl_reg,
/linux-master/arch/arm64/kernel/
H A Dhw_breakpoint.c229 int i, max_slots, ctrl_reg, val_reg, reg_enable; local
235 ctrl_reg = AARCH64_DBG_REG_BCR;
242 ctrl_reg = AARCH64_DBG_REG_WCR;
268 write_wb_reg(ctrl_reg, i,
273 write_wb_reg(ctrl_reg, i, 0);
625 u32 ctrl_reg; local
649 ctrl_reg = read_wb_reg(AARCH64_DBG_REG_BCR, i);
650 decode_ctrl_reg(ctrl_reg, &ctrl);
760 u32 ctrl_reg; local
790 ctrl_reg
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