Lines Matching refs:ctrl_reg
184 * @ctrl_reg: Cached value of the control register.
212 u32 ctrl_reg;
570 unsigned int ctrl_reg;
582 ctrl_reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET);
583 ctrl_reg |= CDNS_I2C_CR_RW | CDNS_I2C_CR_CLR_FIFO;
600 ctrl_reg |= CDNS_I2C_CR_HOLD;
602 cdns_i2c_writereg(ctrl_reg, CDNS_I2C_CR_OFFSET);
624 if (ctrl_reg & CDNS_I2C_CR_HOLD) {
635 ctrl_reg &= ~CDNS_I2C_CR_HOLD;
647 cdns_i2c_writereg(ctrl_reg, CDNS_I2C_CR_OFFSET);
668 unsigned int ctrl_reg;
676 ctrl_reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET);
677 ctrl_reg &= ~CDNS_I2C_CR_RW;
678 ctrl_reg |= CDNS_I2C_CR_CLR_FIFO;
685 ctrl_reg |= CDNS_I2C_CR_HOLD;
686 cdns_i2c_writereg(ctrl_reg, CDNS_I2C_CR_OFFSET);
1079 unsigned int ctrl_reg;
1087 ctrl_reg = id->ctrl_reg;
1088 ctrl_reg &= ~(CDNS_I2C_CR_DIVA_MASK | CDNS_I2C_CR_DIVB_MASK);
1089 ctrl_reg |= ((div_a << CDNS_I2C_CR_DIVA_SHIFT) |
1091 id->ctrl_reg = ctrl_reg;
1092 cdns_i2c_writereg(ctrl_reg, CDNS_I2C_CR_OFFSET);
1094 id->ctrl_reg_diva_divb = ctrl_reg & (CDNS_I2C_CR_DIVA_MASK |
1200 cdns_i2c_writereg(id->ctrl_reg, CDNS_I2C_CR_OFFSET);
1403 id->ctrl_reg = CDNS_I2C_CR_ACK_EN | CDNS_I2C_CR_NEA | CDNS_I2C_CR_MS;