Searched refs:counter_bits (Results 1 - 10 of 10) sorted by relevance

/linux-master/drivers/perf/hisilicon/
H A Dhisi_uncore_pmu.h106 int counter_bits; member in struct:hisi_pmu
H A Dhisi_uncore_pmu.c279 * the PMU. We reduce it to 2^(counter_bits - 1) to account for the
281 * interrupt before another 2^(counter_bits - 1) events occur and the
284 u64 val = BIT_ULL(hisi_pmu->counter_bits - 1);
308 HISI_MAX_PERIOD(hisi_pmu->counter_bits);
H A Dhisi_uncore_ddrc_pmu.c468 ddrc_pmu->counter_bits = 48;
473 ddrc_pmu->counter_bits = 32;
H A Dhisi_uncore_hha_pmu.c480 hha_pmu->counter_bits = 64;
485 hha_pmu->counter_bits = 48;
H A Dhisi_uncore_l3c_pmu.c514 l3c_pmu->counter_bits = 64;
518 l3c_pmu->counter_bits = 48;
H A Dhisi_uncore_cpa_pmu.c289 cpa_pmu->counter_bits = CPA_COUNTER_BITS;
H A Dhisi_uncore_pa_pmu.c470 pa_pmu->counter_bits = 64;
H A Dhisi_uncore_sllc_pmu.c414 sllc_pmu->counter_bits = 64;
H A Dhisi_uncore_uc_pmu.c507 uc_pmu->counter_bits = HISI_UC_CNTR_REG_BITS;
/linux-master/arch/mips/kernel/
H A Dperf_event_mipsxx.c93 static int counter_bits; variable
216 u64 mask = CNTR_BIT_MASK(counter_bits);
256 val &= CNTR_BIT_MASK(counter_bits);
2025 counter_bits = 48;
2030 counter_bits = 64;
2038 counter_bits = 32;
2049 "CPU, irq %d%s\n", mipspmu.name, counters, counter_bits, irq,

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