Searched refs:clock_ctl (Results 1 - 4 of 4) sorted by relevance

/linux-master/arch/mips/ath25/
H A Dar2315.c204 static unsigned __init ar2315_sys_clk(u32 clock_ctl) argument
218 switch (clock_ctl & AR2315_CPUCLK_CLK_SEL_M) {
234 cpu_div = ATH25_REG_MS(clock_ctl, AR2315_CPUCLK_CLK_DIV);
/linux-master/drivers/hid/
H A Dhid-ft260.c148 u8 clock_ctl; /* 0 - 12MHz, 1 - 24MHz, 2 - 48MHz */ member in struct:ft260_get_system_status_report
179 u8 clock_ctl; /* 0 - 12MHz, 1 - 24MHz, 2 - 48MHz */ member in struct:ft260_set_system_clock_report
798 ft260_dbg("clock_ctl: 0x%02x\n", cfg.clock_ctl);
921 FT260_SSTAT_ATTR_SHOW(clock_ctl); variable
922 FT260_BYTE_ATTR_STORE(clock_ctl, ft260_set_system_clock_report,
924 static DEVICE_ATTR_RW(clock_ctl);
/linux-master/drivers/memstick/host/
H A Djmb38x_ms.c679 unsigned int clock_ctl = CLOCK_CONTROL_BY_MMIO, clock_delay = 0; local
725 clock_ctl |= CLOCK_CONTROL_40MHZ;
732 clock_ctl |= CLOCK_CONTROL_40MHZ;
738 clock_ctl |= CLOCK_CONTROL_50MHZ;
745 writel(clock_ctl, host->addr + CLOCK_CONTROL);
/linux-master/drivers/net/ethernet/broadcom/
H A Dtg3.c6134 u32 clock_ctl = tr32(TG3_EAV_REF_CLCK_CTL); local
6136 tw32(TG3_EAV_REF_CLCK_CTL, clock_ctl | TG3_EAV_REF_CLCK_CTL_STOP);
6139 tw32_f(TG3_EAV_REF_CLCK_CTL, clock_ctl | TG3_EAV_REF_CLCK_CTL_RESUME);
6247 u32 clock_ctl; local
6260 clock_ctl = tr32(TG3_EAV_REF_CLCK_CTL);
6261 clock_ctl &= ~TG3_EAV_CTL_TSYNC_GPIO_MASK;
6289 clock_ctl | TG3_EAV_CTL_TSYNC_WDOG0);
6292 tw32(TG3_EAV_REF_CLCK_CTL, clock_ctl);

Completed in 127 milliseconds