Searched refs:clk_period_ps (Results 1 - 4 of 4) sorted by relevance

/linux-master/drivers/memory/samsung/
H A Dexynos5422-dmc.c1029 * @clk_period_ps: the period of the clock, known as tCK
1038 u32 clk_period_ps)
1043 if (clk_period_ps == 0)
1050 val = dmc->timings->tRFC / clk_period_ps;
1051 val += dmc->timings->tRFC % clk_period_ps ? 1 : 0;
1056 val = dmc->timings->tRRD / clk_period_ps;
1057 val += dmc->timings->tRRD % clk_period_ps ? 1 : 0;
1062 val = dmc->timings->tRPab / clk_period_ps;
1063 val += dmc->timings->tRPab % clk_period_ps ? 1 : 0;
1068 val = dmc->timings->tRCD / clk_period_ps;
1036 create_timings_aligned(struct exynos5_dmc *dmc, u32 *reg_timing_row, u32 *reg_timing_data, u32 *reg_timing_power, u32 clk_period_ps) argument
1180 u32 freq_mhz, clk_period_ps; local
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/linux-master/drivers/net/ethernet/microchip/sparx5/
H A Dsparx5_calendar.c287 u32 taxi_bw, clk_period_ps; local
289 clk_period_ps = sparx5_clk_period(sparx5->coreclock);
290 taxi_bw = 128 * 1000000 / clk_period_ps;
291 slow_mode = !!(clk_period_ps > 2000);
365 (adjusted_speed * clk_period_ps);
H A Dsparx5_port.c602 u32 clk_period_ps = 1600; /* 625Mhz for now */ local
624 return urg / clk_period_ps - 1;
/linux-master/drivers/mmc/host/
H A Dsdhci-of-aspeed.c167 u64 clk_period_ps; local
184 clk_period_ps = div_u64(PICOSECONDS_PER_SECOND, (u64)rate_hz);
185 phase_period_ps = div_u64((u64)phase_deg * clk_period_ps, 360ULL);

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