Searched refs:clk_div (Results 1 - 25 of 89) sorted by relevance

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/linux-master/include/linux/dma/
H A Dqcom-gpi-dma.h26 * @clk_div: source clock divider
43 u32 clk_div; member in struct:gpi_spi_config
61 * @clk_div: source clock divider
77 u16 clk_div; member in struct:gpi_i2c_config
/linux-master/drivers/net/ethernet/xilinx/
H A Dll_temac_mdio.c70 int clk_div; local
82 clk_div = 0x3f; /* worst-case default setting */
84 clk_div = bus_hz / (2500 * 1000 * 2) - 1;
85 if (clk_div < 1)
86 clk_div = 1;
87 if (clk_div > 0x3f)
88 clk_div = 0x3f;
94 temac_indirect_out32(lp, XTE_MC_OFFSET, 1 << 6 | clk_div);
H A Dxilinx_axienet_mdio.c162 u32 clk_div; local
198 /* clk_div can be calculated by deriving it from the equation:
199 * fMDIO = fHOST / ((1 + clk_div) * 2)
202 * fHOST / ((1 + clk_div) * 2) <= 2500000
205 * 1 / ((1 + clk_div) * 2) <= (2500000 / fHOST)
208 * 1 / (1 + clk_div) <= ((2500000 * 2) / fHOST)
211 * 1 / (1 + clk_div) <= (5000000 / fHOST)
214 * (1 + clk_div) >= (fHOST / 5000000)
217 * clk_div >= (fHOST / 5000000) - 1
223 clk_div
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/linux-master/include/linux/platform_data/
H A Dshmob_drm.h29 unsigned int clk_div; member in struct:shmob_drm_interface_data
/linux-master/drivers/clk/mxs/
H A Dclk-div.c12 * struct clk_div - mxs integer divider clock
21 struct clk_div { struct
28 static inline struct clk_div *to_clk_div(struct clk_hw *hw)
32 return container_of(divider, struct clk_div, divider);
38 struct clk_div *div = to_clk_div(hw);
46 struct clk_div *div = to_clk_div(hw);
54 struct clk_div *div = to_clk_div(hw);
73 struct clk_div *div;
/linux-master/drivers/pwm/
H A Dpwm-crc.c42 int clk_div; local
44 clk_div = PWM_BASE_CLK_MHZ * period_ns / (256 * NSEC_PER_USEC);
45 /* clk_div 1 - 128, maps to register values 0-127 */
46 if (clk_div > 0)
47 clk_div--;
49 return clk_div;
100 int clk_div = crc_pwm_calc_clk_div(state->period); local
104 clk_div | pwm_output_enable);
127 unsigned int clk_div, clk_div_reg, duty_cycle_reg; local
142 clk_div
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H A Dpwm-mtk-disp.c73 u32 clk_div, period, high_width, value; local
108 * Find period, high_width and clk_div to suit duty_ns and period_ns.
111 * period_ns = 10^9 * (clk_div + 1) * (period + 1) / PWM_CLK_RATE
112 * duty_ns = 10^9 * (clk_div + 1) * high_width / PWM_CLK_RATE
114 * period = (PWM_CLK_RATE * period_ns) / (10^9 * (clk_div + 1)) - 1
115 * high_width = (PWM_CLK_RATE * duty_ns) / (10^9 * (clk_div + 1))
118 clk_div = mul_u64_u64_div_u64(state->period, rate, NSEC_PER_SEC) >>
120 if (clk_div > PWM_CLKDIV_MAX) {
128 div = NSEC_PER_SEC * (clk_div + 1);
151 clk_div << PWM_CLKDIV_SHIF
178 u32 clk_div, pwm_en, con0, con1; local
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/linux-master/drivers/mfd/
H A Dfsl-imx25-tsadc.c103 unsigned clk_div; local
115 clk_div = DIV_ROUND_UP(clk_get_rate(tsadc->clk), 1750000);
116 dev_dbg(&pdev->dev, "Setting up ADC clock divider to %u\n", clk_div);
119 clk_div -= 2;
120 clk_div /= 2;
126 clk_div = max_t(unsigned, 4, clk_div);
129 clk_get_rate(tsadc->clk) / (2 * clk_div + 2));
133 MX25_TGCR_ADCCLKCFG(clk_div));
/linux-master/drivers/media/dvb-frontends/
H A Dstv6110.h31 u8 clk_div; /* divisor value for the output clock */ member in struct:stv6110_config
H A Dstv6110x.h17 u8 clk_div; /* divisor value for the output clock */ member in struct:stv6110x_config
/linux-master/arch/mips/ath25/
H A Dar2315.c208 unsigned int clk_div; local
221 clk_div = ATH25_REG_MS(pllc_ctrl, AR2315_PLLC_CLKM_DIV);
222 clk_div = pllc_divide_table[clk_div];
225 clk_div = ATH25_REG_MS(pllc_ctrl, AR2315_PLLC_CLKC_DIV);
226 clk_div = pllc_divide_table[clk_div];
230 clk_div = 1;
237 return pllc_out / (clk_div * cpu_div);
/linux-master/drivers/i2c/busses/
H A Di2c-pasemi-core.h18 unsigned int clk_div; member in struct:pasemi_smbus
H A Di2c-sun6i-p2wi.c192 int clk_div; local
286 clk_div = parent_clk_freq / clk_freq;
287 if (!clk_div) {
291 clk_div = 1;
292 } else if (clk_div > P2WI_CCR_MAX_CLK_DIV) {
296 clk_div = P2WI_CCR_MAX_CLK_DIV;
299 writel(P2WI_CCR_SDA_OUT_DELAY(1) | P2WI_CCR_CLK_DIV(clk_div),
H A Di2c-pasemi-platform.c32 data->smbus.clk_div = DIV_ROUND_UP(clk_rate, 16 * frequency);
33 if (data->smbus.clk_div < 4)
37 if (data->smbus.clk_div > 0xff)
H A Di2c-mt7621.c65 u32 clk_div; member in struct:mtk_i2c
96 iowrite32(((i2c->clk_div << 16) & SM0CTL0_CLK_DIV_MASK) | SM0CTL0_EN |
263 i2c->clk_div = clk_get_rate(i2c->clk) / i2c->bus_freq - 1;
264 if (i2c->clk_div < 99)
265 i2c->clk_div = 99;
266 if (i2c->clk_div > SM0CTL0_CLK_DIV_MAX)
267 i2c->clk_div = SM0CTL0_CLK_DIV_MAX;
H A Di2c-pasemi-pci.c43 smbus->clk_div = CLK_100K_DIV;
/linux-master/drivers/gpu/drm/renesas/shmobile/
H A Dshmob_drm_drv.h25 unsigned int clk_div; member in struct:shmob_drm_config
/linux-master/drivers/spi/
H A Dspi-hisi-kunpeng.c117 u16 clk_div; /* baud rate divider */ member in struct:hisi_chip_data
119 /* clk_div = (1 + div_post) * div_pre */
282 if (chip->clk_div % chip->div_pre == 0)
288 if (chip->div_pre > chip->clk_div)
289 chip->div_pre = chip->clk_div;
291 chip->div_post = (chip->clk_div / chip->div_pre) - 1;
300 chip->clk_div = DIV_ROUND_UP(host->max_speed_hz, speed_hz) + 1;
301 chip->clk_div &= 0xfffe;
302 if (chip->clk_div > CLK_DIV_MAX)
303 chip->clk_div
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H A Dspi-axi-spi-engine.c208 unsigned int clk_div, max_hz = msg->spi->controller->max_speed_hz; local
212 clk_div = DIV_ROUND_UP(max_hz, xfer->speed_hz);
213 xfer->effective_speed_hz = max_hz / min(clk_div, 256U);
223 int clk_div, new_clk_div; local
227 clk_div = 1;
238 if (new_clk_div != clk_div) {
239 clk_div = new_clk_div;
243 clk_div - 1));
284 if (clk_div != 1)
/linux-master/sound/soc/ti/
H A Ddavinci-i2s.c161 int clk_div; member in struct:davinci_mcbsp_dev
372 dev->clk_div = div;
383 unsigned int rcr, xcr, srgr, clk_div, freq, framesize; local
410 clk_div = 256;
412 framesize = (freq / (--clk_div)) /
416 (clk_div));
417 clk_div--;
421 clk_div = freq / (mcbsp_word_length * 16) /
426 clk_div &= 0xFF;
427 srgr |= clk_div;
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/linux-master/drivers/clk/
H A Dclk-versaclock3.c587 static struct vc3_hw_data clk_div[5]; variable in typeref:struct:vc3_hw_data
591 { .hw = &clk_div[VC3_DIV2].hw }
791 static struct vc3_hw_data clk_div[] = { variable in typeref:struct:vc3_hw_data
894 &clk_div[VC3_DIV5].hw,
895 &clk_div[VC3_DIV4].hw
910 &clk_div[VC3_DIV5].hw,
911 &clk_div[VC3_DIV4].hw
926 &clk_div[VC3_DIV2].hw,
927 &clk_div[VC3_DIV4].hw
942 &clk_div[VC3_DIV
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/linux-master/drivers/bus/
H A Dsunxi-rsb.c655 int clk_div, ret; local
682 clk_div = p_clk_freq / rsb->clk_freq / 2;
683 if (!clk_div)
684 clk_div = 1;
685 else if (clk_div > RSB_CCR_MAX_CLK_DIV + 1)
686 clk_div = RSB_CCR_MAX_CLK_DIV + 1;
688 clk_delay = clk_div >> 1;
692 dev_info(dev, "RSB running at %lu Hz\n", p_clk_freq / clk_div / 2);
693 writel(RSB_CCR_SDA_OUT_DELAY(clk_delay) | RSB_CCR_CLK_DIV(clk_div - 1),
/linux-master/arch/mips/cavium-octeon/executive/
H A Dcvmx-helper-jtag.c63 jtgc.s.clk_div = clock_div;
/linux-master/drivers/leds/
H A Dleds-bcm6358.c154 u32 clk_div; local
170 of_property_read_u32(np, "brcm,clk-div", &clk_div);
171 switch (clk_div) {
/linux-master/sound/soc/xilinx/
H A Dxlnx_spdif.c109 u32 val, clk_div, clk_cfg; local
112 clk_div = DIV_ROUND_CLOSEST(ctx->aclk, MAX_CHANNELS * AES_SAMPLE_WIDTH *
115 switch (clk_div) {

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