Searched refs:cfg_base (Results 1 - 16 of 16) sorted by relevance

/linux-master/arch/mips/pci/
H A Dops-lantiq.c29 unsigned long cfg_base; local
41 cfg_base = (unsigned long) ltq_pci_mapped_cfg;
42 cfg_base |= (bus->number << LTQ_PCI_CFG_BUSNUM_SHF) | (devfn <<
47 ltq_w32(swab32(*data), ((u32 *)cfg_base));
49 *data = ltq_r32(((u32 *)(cfg_base)));
55 cfg_base = (unsigned long) ltq_pci_mapped_cfg;
56 cfg_base |= (0x0 << LTQ_PCI_CFG_FUNNUM_SHF) + 4;
57 temp = ltq_r32(((u32 *)(cfg_base)));
59 cfg_base = (unsigned long) ltq_pci_mapped_cfg;
60 cfg_base |
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H A Dpci-ar71xx.c49 void __iomem *cfg_base; member in struct:ar71xx_pci_controller
109 void __iomem *base = apc->cfg_base;
147 void __iomem *base = apc->cfg_base;
164 void __iomem *base = apc->cfg_base;
180 void __iomem *base = apc->cfg_base;
204 void __iomem *base = apc->cfg_base;
339 apc->cfg_base = devm_platform_ioremap_resource_byname(pdev,
340 "cfg_base");
341 if (IS_ERR(apc->cfg_base))
342 return PTR_ERR(apc->cfg_base);
[all...]
H A Dpci-alchemy.c105 unsigned long offset, status, cfg_base, flags, entryLo0, entryLo1, r; local
130 cfg_base = (1 << device) << 11;
132 cfg_base = 0x80000000 | (bus->number << 16) | (device << 11);
137 offset |= cfg_base & ~PAGE_MASK;
140 cfg_base = cfg_base & PAGE_MASK;
145 entryLo0 = (6 << 26) | (cfg_base >> 6) | (2 << 3) | 7;
146 entryLo1 = (6 << 26) | (cfg_base >> 6) | (0x1000 >> 6) | (2 << 3) | 7;
/linux-master/drivers/net/can/sja1000/
H A Dpeak_pci.c37 void __iomem *cfg_base; /* Common for all channels */ member in struct:peak_pci_chan
162 void __iomem *cfg_base; /* Common for all channels */ member in struct:peak_pciec_card
180 u8 gp_outen = readb(card->cfg_base + PITA_GPOEN) & ~PITA_GPIN_SCL;
182 writeb(gp_outen, card->cfg_base + PITA_GPOEN);
187 u8 gp_outen = readb(card->cfg_base + PITA_GPOEN) & ~PITA_GPIN_SDA;
189 writeb(gp_outen, card->cfg_base + PITA_GPOEN);
205 gp_out = readb(card->cfg_base + PITA_GPOUT) & ~PITA_GPIN_SDA;
206 writeb(gp_out, card->cfg_base + PITA_GPOUT);
209 gp_outen = readb(card->cfg_base + PITA_GPOEN);
215 writeb(gp_outen, card->cfg_base
556 void __iomem *cfg_base, *reg_base; local
744 void __iomem *cfg_base = chan->cfg_base; local
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/linux-master/sound/soc/intel/avs/
H A Dpath.c245 cfg->base.cpc = t->cfg_base->cpc;
246 cfg->base.ibs = t->cfg_base->ibs;
247 cfg->base.obs = t->cfg_base->obs;
248 cfg->base.is_pages = t->cfg_base->is_pages;
310 cfg->base.cpc = t->cfg_base->cpc;
311 cfg->base.ibs = t->cfg_base->ibs;
312 cfg->base.obs = t->cfg_base->obs;
313 cfg->base.is_pages = t->cfg_base->is_pages;
332 cfg.base.cpc = t->cfg_base->cpc;
333 cfg.base.ibs = t->cfg_base
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H A Dtopology.h191 struct avs_tplg_modcfg_base *cfg_base; member in struct:avs_tplg_module
H A Dtopology.c1088 .offset = offsetof(struct avs_tplg_module, cfg_base),
/linux-master/drivers/perf/
H A Dalibaba_uncore_drw_pmu.c94 void __iomem *cfg_base; member in struct:ali_drw_pmu
294 cycle_high = readl(drw_pmu->cfg_base + ALI_DRW_PMU_CYCLE_CNT_HIGH);
296 cycle_low = readl(drw_pmu->cfg_base + ALI_DRW_PMU_CYCLE_CNT_LOW);
301 return readl(drw_pmu->cfg_base +
331 drw_pmu->cfg_base + ALI_DRW_PMU_TEST_CTRL);
335 writel(pre_val, drw_pmu->cfg_base + ALI_DRW_PMU_CNT_PRELOAD);
339 writel(0x0, drw_pmu->cfg_base + ALI_DRW_PMU_TEST_CTRL);
349 val = readl(drw_pmu->cfg_base + reg);
357 writel(val, drw_pmu->cfg_base + reg);
367 val = readl(drw_pmu->cfg_base
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/linux-master/drivers/pci/controller/
H A Dpci-xgene.c66 void __iomem *cfg_base; member in struct:xgene_pcie
107 return port->cfg_base + AXI_EP_CFG_ACCESS;
109 return port->cfg_base;
246 port->cfg_base = cfg->win;
356 port->cfg_base = devm_ioremap_resource(dev, res);
357 if (IS_ERR(port->cfg_base))
358 return PTR_ERR(port->cfg_base);
483 void __iomem *cfg_base = port->cfg_base; local
508 bar_addr = cfg_base
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/linux-master/drivers/pci/controller/dwc/
H A Dpci-meson.c69 void __iomem *cfg_base; member in struct:meson_pcie
117 mp->cfg_base = devm_platform_ioremap_resource_byname(pdev, "cfg");
118 if (IS_ERR(mp->cfg_base))
119 return PTR_ERR(mp->cfg_base);
224 return readl(mp->cfg_base + reg);
229 writel(val, mp->cfg_base + reg);
/linux-master/drivers/gpu/drm/i915/gvt/
H A Dcfg_space.c72 u8 *cfg_base = vgpu_cfg_space(vgpu); local
79 old = cfg_base[off + i];
90 cfg_base[off + i] = (old & ~mask) | new;
95 memcpy(cfg_base + off + i, src + i, bytes - i);
/linux-master/include/linux/
H A Dpruss_driver.h87 * @cfg_base: base iomap for CFG region
97 void __iomem *cfg_base; member in struct:pruss
/linux-master/drivers/pci/controller/cadence/
H A Dpcie-cadence-host.c73 return rc->cfg_base + (where & 0xfff);
531 rc->cfg_base = devm_pci_remap_cfg_resource(dev, res);
532 if (IS_ERR(rc->cfg_base))
533 return PTR_ERR(rc->cfg_base);
H A Dpcie-cadence.h320 * @cfg_base: IO mapped window to access the PCI configuration space of a
332 void __iomem *cfg_base; member in struct:cdns_pcie_rc
/linux-master/drivers/soc/ti/
H A Dpruss.c348 reg = pruss->cfg_base + reg_offset;
442 pruss->cfg_base = devm_ioremap(dev, res.start, resource_size(&res));
443 if (!pruss->cfg_base) {
452 pruss->cfg_regmap = devm_regmap_init_mmio(dev, pruss->cfg_base,
/linux-master/drivers/net/usb/
H A Dsmsc75xx.c1536 int cfg_base = WUF_CFGX + filter * 4; local
1540 ret = smsc75xx_write_reg(dev, cfg_base, wuf_cfg);

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