can/sja1000/peak_pci.c

37 	void __iomem *cfg_base;		/* Common for all channels */
162 	void __iomem *cfg_base;		/* Common for all channels */
180 	u8 gp_outen = readb(card->cfg_base + PITA_GPOEN) & ~PITA_GPIN_SCL;
182 	writeb(gp_outen, card->cfg_base + PITA_GPOEN);
187 	u8 gp_outen = readb(card->cfg_base + PITA_GPOEN) & ~PITA_GPIN_SDA;
189 	writeb(gp_outen, card->cfg_base + PITA_GPOEN);
205 	gp_out = readb(card->cfg_base + PITA_GPOUT) & ~PITA_GPIN_SDA;
206 	writeb(gp_out, card->cfg_base + PITA_GPOUT);
209 	gp_outen = readb(card->cfg_base + PITA_GPOEN);
215 	writeb(gp_outen, card->cfg_base + PITA_GPOEN);
224 	gp_out = readb(card->cfg_base + PITA_GPOUT) & ~PITA_GPIN_SCL;
225 	writeb(gp_out, card->cfg_base + PITA_GPOUT);
228 	gp_outen = readb(card->cfg_base + PITA_GPOEN);
234 	writeb(gp_outen, card->cfg_base + PITA_GPOEN);
244 	return (readb(card->cfg_base + PITA_GPIN) & PITA_GPIN_SDA) ? 1 : 0;
254 	return (readb(card->cfg_base + PITA_GPIN) & PITA_GPIN_SCL) ? 1 : 0;
459 		card->cfg_base = chan->cfg_base;
546 	icr = readw(chan->cfg_base + PITA_ICR);
548 		writew(chan->icr_mask, chan->cfg_base + PITA_ICR);
556 	void __iomem *cfg_base, *reg_base;
589 	cfg_base = pci_iomap(pdev, 0, PEAK_PCI_CFG_SIZE);
590 	if (!cfg_base) {
604 	writew(0x0005, cfg_base + PITA_GPIOICR + 2);
606 	writeb(0x00, cfg_base + PITA_GPIOICR);
608 	writeb(0x05, cfg_base + PITA_MISC + 3);
611 	writeb(0x04, cfg_base + PITA_MISC + 3);
614 	if (readl(cfg_base + PEAK_VER_REG1)) {
616 		u32 fw_ver = readl(cfg_base + PEAK_VER_REG2);
628 	icr = readw(cfg_base + PITA_ICR + 2);
640 		chan->cfg_base = cfg_base;
690 			 "%s at reg_base=0x%p cfg_base=0x%p irq=%d\n",
691 			 dev->name, priv->reg_base, chan->cfg_base, dev->irq);
695 	writew(icr, cfg_base + PITA_ICR + 2);
705 	writew(0x0, cfg_base + PITA_ICR + 2);
724 	pci_iounmap(pdev, cfg_base);
744 	void __iomem *cfg_base = chan->cfg_base;
748 	writew(0x0, cfg_base + PITA_ICR + 2);
769 	pci_iounmap(pdev, cfg_base);