| /linux-master/drivers/gpu/drm/radeon/ |
| H A D | evergreen_cs.c | 176 unsigned bankw; member in struct:eg_surface
268 palign = (8 * surf->bankw * track->npipes) * surf->mtilea;
347 switch (surf->bankw) {
348 case 0: surf->bankw = 1; break;
349 case 1: surf->bankw = 2; break;
350 case 2: surf->bankw = 4; break;
351 case 3: surf->bankw = 8; break;
353 dev_warn(p->dev, "%s:%d %s invalid bankw %d\n",
354 __func__, __LINE__, prefix, surf->bankw);
410 surf.bankw
1182 unsigned bankw, bankh, mtaspect, tile_split; local
1446 unsigned bankw, bankh, mtaspect, tile_split; local
1474 unsigned bankw, bankh, mtaspect, tile_split; local
2363 unsigned bankw, bankh, mtaspect, tile_split; local
[all...] |
| H A D | radeon_object.c | 616 unsigned bankw, bankh, mtaspect, tilesplit, stilesplit; local
618 bankw = (tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK;
623 switch (bankw) {
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| H A D | atombios_crtc.c | 1146 unsigned bankw, bankh, mtaspect, tile_split; local
1266 evergreen_tiling_fields(tiling_flags, &bankw, &bankh, &mtaspect, &tile_split);
1332 fb_format |= EVERGREEN_GRPH_BANK_WIDTH(bankw);
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| H A D | evergreen.c | 1111 void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw, argument
1115 *bankw = (tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK;
1119 switch (*bankw) {
1121 case 1: *bankw = EVERGREEN_ADDR_SURF_BANK_WIDTH_1; break;
1122 case 2: *bankw = EVERGREEN_ADDR_SURF_BANK_WIDTH_2; break;
1123 case 4: *bankw = EVERGREEN_ADDR_SURF_BANK_WIDTH_4; break;
1124 case 8: *bankw = EVERGREEN_ADDR_SURF_BANK_WIDTH_8; break;
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| H A D | radeon.h | 356 extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
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| /linux-master/drivers/gpu/drm/amd/display/amdgpu_dm/ |
| H A D | amdgpu_dm_plane.c | 185 unsigned int bankw, bankh, mtaspect, tile_split, num_banks; local
187 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
198 tiling_info->gfx8.bank_width = bankw;
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| /linux-master/drivers/gpu/drm/amd/amdgpu/ |
| H A D | dce_v11_0.c | 2036 unsigned bankw, bankh, mtaspect, tile_split, num_banks; local
2038 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
2049 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_WIDTH, bankw);
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| H A D | dce_v10_0.c | 1986 unsigned bankw, bankh, mtaspect, tile_split, num_banks; local
1988 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
1999 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_WIDTH, bankw);
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| H A D | dce_v8_0.c | 1925 unsigned bankw, bankh, mtaspect, tile_split, num_banks; local
1927 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
1936 fb_format |= (bankw << GRPH_CONTROL__GRPH_BANK_WIDTH__SHIFT);
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| H A D | dce_v6_0.c | 1956 unsigned bankw, bankh, mtaspect, tile_split, num_banks; local
1958 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
1967 fb_format |= GRPH_BANK_WIDTH(bankw);
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